Simulation Results: alert_handler

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.12 %
  • code
  • 90.46 %
  • assert
  • 98.02 %
  • func
  • 75.88 %
  • line
  • 99.67 %
  • branch
  • 98.16 %
  • cond
  • 91.84 %
  • toggle
  • 90.05 %
  • FSM
  • 72.58 %
Validation stages
V1
100.00%
V2
89.47%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 63.930s 1729.831us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 4.500s 73.077us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.550s 290.670us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 558.390s 70954.044us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 225.490s 4464.401us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.840s 43.349us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.550s 290.670us 1 1 100.00
alert_handler_csr_aliasing 225.490s 4464.401us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 124.260s 4236.213us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 15.010s 336.743us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1013.290s 65212.284us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 21.260s 287.769us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 63.930s 1729.831us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 6.130s 260.045us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 45.540s 4091.515us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 146.000s 44146.694us 1 1 100.00
lpg 1 2 50.00
alert_handler_lpg 2551.130s 1000000.000us 0 1 0.00
alert_handler_lpg_stub_clk 2616.910s 70817.036us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1942.000s 113745.304us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 15.290s 1090.662us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 4.000s 65.484us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 2.110s 11.132us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 6.950s 162.510us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 6.950s 162.510us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 4.500s 73.077us 1 1 100.00
alert_handler_csr_rw 4.550s 290.670us 1 1 100.00
alert_handler_csr_aliasing 225.490s 4464.401us 1 1 100.00
alert_handler_same_csr_outstanding 17.730s 718.081us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 4.500s 73.077us 1 1 100.00
alert_handler_csr_rw 4.550s 290.670us 1 1 100.00
alert_handler_csr_aliasing 225.490s 4464.401us 1 1 100.00
alert_handler_same_csr_outstanding 17.730s 718.081us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 260.750s 5768.745us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 260.750s 5768.745us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 260.750s 5768.745us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 260.750s 5768.745us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 239.070s 10582.599us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 19.180s 1656.077us 1 1 100.00
alert_handler_tl_intg_err 2.120s 38.918us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.120s 38.918us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 260.750s 5768.745us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 63.930s 1729.831us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 63.930s 1729.831us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 63.930s 1729.831us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 63.930s 1729.831us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 21.260s 287.769us 1 1 100.00
sec_cm_lpg_intersig_mubi 0 1 0.00
alert_handler_lpg 2551.130s 1000000.000us 0 1 0.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 21.260s 287.769us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1013.290s 65212.284us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1013.290s 65212.284us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 19.180s 1656.077us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 19.180s 1656.077us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 19.180s 1656.077us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 19.180s 1656.077us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 19.180s 1656.077us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 19.180s 1656.077us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 19.180s 1656.077us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 19.180s 1656.077us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 19.180s 1656.077us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 55.990s 958.621us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
alert_handler_lpg 87680187956386214801568370702955953803405567816242401312340018318361325888273 80
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 30498588757814106092909227616348901212741431575633928393245881095544559056148 222
UVM_INFO @ 1090661952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 75443986302970824063428783461448469443100540569361182305611716269315436113669 118
UVM_INFO @ 958621428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---