Simulation Results: clkmgr

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.26 %
  • code
  • 69.63 %
  • assert
  • 89.46 %
  • func
  • 63.69 %
  • line
  • 82.32 %
  • branch
  • 87.53 %
  • cond
  • 78.50 %
  • toggle
  • 99.81 %
  • FSM
  • 0.00 %
Validation stages
V1
33.33%
V2
53.85%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.990s 30.733us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.150s 28.233us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 1.150s 20.789us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 5.710s 496.530us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.840s 6.594us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.160s 18.921us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 1.150s 20.789us 0 1 0.00
clkmgr_csr_aliasing 0.840s 6.594us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.050s 35.906us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.270s 45.804us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.890s 17.567us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.990s 30.733us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.920s 6.848us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.610s 2.830us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.920s 6.848us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.790s 18.674us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.970s 21.209us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 5.610s 472.879us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 5.610s 472.879us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 1.150s 28.233us 1 1 100.00
clkmgr_csr_rw 1.150s 20.789us 0 1 0.00
clkmgr_csr_aliasing 0.840s 6.594us 0 1 0.00
clkmgr_same_csr_outstanding 1.030s 12.903us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 1.150s 28.233us 1 1 100.00
clkmgr_csr_rw 1.150s 20.789us 0 1 0.00
clkmgr_csr_aliasing 0.840s 6.594us 0 1 0.00
clkmgr_same_csr_outstanding 1.030s 12.903us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 3.950s 410.095us 1 1 100.00
clkmgr_tl_intg_err 0.850s 3.539us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.340s 82.638us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.340s 82.638us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.340s 82.638us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.340s 82.638us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.750s 5.377us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.850s 3.539us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.920s 6.848us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.610s 2.830us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.340s 82.638us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.120s 40.659us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 1.150s 20.789us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 3.950s 410.095us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 1.150s 20.789us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 1.150s 20.789us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 3.950s 410.095us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.710s 6.268us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 5.840s 479.450us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency 86896930672404805468806924300016176801577369329733397742851535467958241499772 76
UVM_INFO @ 6847710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 89641624667568030923840323567680437909287928336615133691433132484820007943600 79
UVM_INFO @ 479450467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 49689847561004538925132931426059340764053939078998290273891620159056441707524 78
UVM_INFO @ 18674446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 47592041424332315623664409415051545473481479255418519553301416383070765038575 75
UVM_INFO @ 5377367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 13903733625648585483826125463434675999063667311653299867998476672989916760619 75
UVM_INFO @ 3539376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 83089579080831649122024520788891203887057914919645946651417425068246382970774 76
UVM_INFO @ 20789333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_csr_aliasing 4785195460485703046130955573687738897193685328621128236527574679552859024529 75
UVM_INFO @ 6594092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 79454978700027798294914446477323968616331210544773644430000287006540340623879 76
UVM_INFO @ 18920608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency_timeout 40563011778305785618206466398540017218751394618796735669296304529073636512823 77
UVM_INFO @ 2829531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 112128250924945486174794683001515811512707591138098589179665026480415751481100 74
UVM_INFO @ 6267838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 79976055465567430531464879424188921026123950128289175110710417916791421586175 75
UVM_INFO @ 496529615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 97217886796161329275731402892576777086140858066334180134770936235581803522632 75
UVM_INFO @ 12903084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---