Simulation Results: csrng

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.80 %
  • code
  • 92.22 %
  • assert
  • 93.67 %
  • func
  • 71.51 %
  • block
  • 96.85 %
  • line
  • 97.62 %
  • branch
  • 92.18 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 1.000s 16.142us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 24.306us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 47.280us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 23.000s 1998.371us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 5.000s 199.785us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 54.239us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 47.280us 1 1 100.00
csrng_csr_aliasing 5.000s 199.785us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 82.434us 1 1 100.00
alerts 1 1 100.00
csrng_alert 6.000s 345.236us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 40.643us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 2.000s 53.991us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 2.000s 53.991us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 401.000s 38303.732us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 15.512us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 15.771us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 5.000s 175.108us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 5.000s 175.108us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 24.306us 1 1 100.00
csrng_csr_rw 2.000s 47.280us 1 1 100.00
csrng_csr_aliasing 5.000s 199.785us 1 1 100.00
csrng_same_csr_outstanding 3.000s 56.589us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 24.306us 1 1 100.00
csrng_csr_rw 2.000s 47.280us 1 1 100.00
csrng_csr_aliasing 5.000s 199.785us 1 1 100.00
csrng_same_csr_outstanding 3.000s 56.589us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 5.000s 174.052us 1 1 100.00
csrng_tl_intg_err 6.000s 227.974us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 37.230us 1 1 100.00
csrng_csr_rw 2.000s 47.280us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 6.000s 345.236us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 401.000s 38303.732us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 82.434us 1 1 100.00
csrng_err 2.000s 40.643us 1 1 100.00
csrng_sec_cm 5.000s 174.052us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 82.434us 1 1 100.00
csrng_err 2.000s 40.643us 1 1 100.00
csrng_sec_cm 5.000s 174.052us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 82.434us 1 1 100.00
csrng_err 2.000s 40.643us 1 1 100.00
csrng_sec_cm 5.000s 174.052us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 82.434us 1 1 100.00
csrng_err 2.000s 40.643us 1 1 100.00
csrng_sec_cm 5.000s 174.052us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 82.434us 1 1 100.00
csrng_err 2.000s 40.643us 1 1 100.00
csrng_sec_cm 5.000s 174.052us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 6.000s 345.236us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 82.434us 1 1 100.00
csrng_err 2.000s 40.643us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 401.000s 38303.732us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 6.000s 345.236us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 6.000s 227.974us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 82.434us 1 1 100.00
csrng_err 2.000s 40.643us 1 1 100.00
csrng_sec_cm 5.000s 174.052us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 82.434us 1 1 100.00
csrng_err 2.000s 40.643us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 82.434us 1 1 100.00
csrng_err 2.000s 40.643us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 82.434us 1 1 100.00
csrng_err 2.000s 40.643us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 82.434us 1 1 100.00
csrng_err 2.000s 40.643us 1 1 100.00
csrng_sec_cm 5.000s 174.052us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 82.434us 1 1 100.00
csrng_err 2.000s 40.643us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:640) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*]) 1 test run
csrng_cmds 75183287675724099189774158169024004629598476129455778461956381855902316951397 109
UVM_INFO @ 53991001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 31887984388144018069314387529911017812085023780857943957678167770293508096808 None