Simulation Results: edn/edn0

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 80.28 %
  • code
  • 93.21 %
  • assert
  • 97.57 %
  • func
  • 50.07 %
  • block
  • 96.56 %
  • line
  • 98.49 %
  • branch
  • 92.36 %
  • toggle
  • 82.77 %
  • FSM
  • 99.22 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 48.305us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 12.917us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 13.060us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.000s 1045.630us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 3.000s 36.497us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 31.622us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 13.060us 1 1 100.00
edn_csr_aliasing 3.000s 36.497us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 3.000s 49.108us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 3.000s 49.108us 1 1 100.00
genbits 1 1 100.00
edn_genbits 3.000s 49.108us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 28.893us 1 1 100.00
alerts 1 1 100.00
edn_alert 4.000s 365.331us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 21.646us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 50.506us 1 1 100.00
edn_disable_auto_req_mode 2.000s 72.402us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.000s 207.695us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 50.770us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 27.235us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.000s 247.793us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.000s 247.793us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 12.917us 1 1 100.00
edn_csr_rw 2.000s 13.060us 1 1 100.00
edn_csr_aliasing 3.000s 36.497us 1 1 100.00
edn_same_csr_outstanding 2.000s 38.139us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 12.917us 1 1 100.00
edn_csr_rw 2.000s 13.060us 1 1 100.00
edn_csr_aliasing 3.000s 36.497us 1 1 100.00
edn_same_csr_outstanding 2.000s 38.139us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.000s 254.040us 1 1 100.00
edn_tl_intg_err 2.000s 196.022us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 28.112us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 4.000s 365.331us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 254.040us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 254.040us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 254.040us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 254.040us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 4.000s 365.331us 1 1 100.00
edn_sec_cm 4.000s 254.040us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 4.000s 365.331us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 196.022us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 45.000s 4564.730us 1 1 100.00