Simulation Results: edn/edn1

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.19 %
  • code
  • 83.14 %
  • assert
  • 97.14 %
  • func
  • 81.30 %
  • line
  • 98.25 %
  • branch
  • 93.51 %
  • cond
  • 88.77 %
  • toggle
  • 87.42 %
  • FSM
  • 47.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.970s 52.967us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.950s 56.487us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.790s 54.968us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.940s 169.691us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.240s 138.996us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 31.854us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.790s 54.968us 1 1 100.00
edn_csr_aliasing 1.240s 138.996us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.170s 40.699us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.170s 40.699us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.170s 40.699us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 21.938us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.020s 29.688us 1 1 100.00
errs 1 1 100.00
edn_err 1.070s 67.139us 1 1 100.00
disable 2 2 100.00
edn_disable 0.820s 11.425us 1 1 100.00
edn_disable_auto_req_mode 1.260s 44.430us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.920s 801.592us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 22.923us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.910s 13.518us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.970s 433.500us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.970s 433.500us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.950s 56.487us 1 1 100.00
edn_csr_rw 0.790s 54.968us 1 1 100.00
edn_csr_aliasing 1.240s 138.996us 1 1 100.00
edn_same_csr_outstanding 0.930s 15.366us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.950s 56.487us 1 1 100.00
edn_csr_rw 0.790s 54.968us 1 1 100.00
edn_csr_aliasing 1.240s 138.996us 1 1 100.00
edn_same_csr_outstanding 0.930s 15.366us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.190s 1228.241us 1 1 100.00
edn_tl_intg_err 2.050s 103.152us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 53.070us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.020s 29.688us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.190s 1228.241us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.190s 1228.241us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.190s 1228.241us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.190s 1228.241us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.020s 29.688us 1 1 100.00
edn_sec_cm 2.190s 1228.241us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.020s 29.688us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.050s 103.152us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 46.180s 11831.761us 1 1 100.00