Simulation Results: entropy_src/rng_16bits

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 69.02 %
  • code
  • 81.75 %
  • assert
  • 73.08 %
  • func
  • 52.23 %
  • block
  • 93.99 %
  • line
  • 97.75 %
  • branch
  • 85.79 %
  • toggle
  • 52.83 %
  • FSM
  • 90.62 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 18.725us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 53.700us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 58.063us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 16.000s 915.665us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 258.769us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 10.511us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 58.063us 1 1 100.00
entropy_src_csr_aliasing 3.000s 258.769us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 18.725us 1 1 100.00
entropy_src_rng 267.000s 13045.311us 1 1 100.00
entropy_src_fw_ov 159.000s 13098.918us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 159.000s 13098.918us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 267.000s 13045.311us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 399.000s 14023.657us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 267.000s 13045.311us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 267.000s 13045.311us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 267.000s 13045.311us 1 1 100.00
entropy_src_intr 16.000s 1028.243us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 267.000s 13045.311us 1 1 100.00
entropy_src_functional_alerts 8.000s 177.465us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 299.000s 13207.630us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 44.196us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 2.000s 60.162us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 23.406us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 1.000s 18.387us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 179.002us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 179.002us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 53.700us 1 1 100.00
entropy_src_csr_rw 1.000s 58.063us 1 1 100.00
entropy_src_csr_aliasing 3.000s 258.769us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 32.668us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 53.700us 1 1 100.00
entropy_src_csr_rw 1.000s 58.063us 1 1 100.00
entropy_src_csr_aliasing 3.000s 258.769us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 32.668us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 4.000s 269.119us 1 1 100.00
entropy_src_tl_intg_err 3.000s 384.718us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 267.000s 13045.311us 1 1 100.00
entropy_src_cfg_regwen 1.000s 16.263us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 267.000s 13045.311us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 267.000s 13045.311us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 267.000s 13045.311us 1 1 100.00
entropy_src_fw_ov 159.000s 13098.918us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 44.196us 1 1 100.00
entropy_src_sec_cm 4.000s 269.119us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 44.196us 1 1 100.00
entropy_src_sec_cm 4.000s 269.119us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 267.000s 13045.311us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 44.196us 1 1 100.00
entropy_src_sec_cm 4.000s 269.119us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 44.196us 1 1 100.00
entropy_src_sec_cm 4.000s 269.119us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 44.196us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 8.000s 177.465us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 384.718us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 93.000s 13171.433us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 12.000s 338.086us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_hi_threshold 1 test run
entropy_src_stress_all_with_rand_reset 115451961159826291421271479126502744580904091860909785837899722311470662475210 131
UVM_INFO @ 338085634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_hi_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 88087507899199525392724518507094160986271142267570902405730489458571491170449 113
UVM_INFO @ 10510785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---