Simulation Results: hmac

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.14 %
  • code
  • 95.95 %
  • assert
  • 97.17 %
  • func
  • 29.28 %
  • block
  • 97.46 %
  • line
  • 98.39 %
  • branch
  • 93.64 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 15.000s 1562.733us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 92.824us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 137.675us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 14.000s 2016.237us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 56.178us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 107.707us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 137.675us 1 1 100.00
hmac_csr_aliasing 3.000s 56.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 21.000s 4938.023us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 48.000s 4974.443us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 11.000s 239.910us 1 1 100.00
hmac_test_sha384_vectors 428.000s 17674.181us 1 1 100.00
hmac_test_sha512_vectors 427.000s 74331.821us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 325.589us 1 1 100.00
hmac_test_hmac384_vectors 11.000s 614.522us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 762.537us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 30.000s 30289.828us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 25.000s 2989.683us 1 1 100.00
error 1 1 100.00
hmac_error 35.000s 12880.330us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 69.000s 2307.685us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 15.000s 1562.733us 1 1 100.00
hmac_long_msg 21.000s 4938.023us 1 1 100.00
hmac_back_pressure 48.000s 4974.443us 1 1 100.00
hmac_datapath_stress 25.000s 2989.683us 1 1 100.00
hmac_burst_wr 30.000s 30289.828us 1 1 100.00
hmac_stress_all 424.000s 87774.464us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 15.000s 1562.733us 1 1 100.00
hmac_long_msg 21.000s 4938.023us 1 1 100.00
hmac_back_pressure 48.000s 4974.443us 1 1 100.00
hmac_datapath_stress 25.000s 2989.683us 1 1 100.00
hmac_wipe_secret 69.000s 2307.685us 1 1 100.00
hmac_test_sha256_vectors 11.000s 239.910us 1 1 100.00
hmac_test_sha384_vectors 428.000s 17674.181us 1 1 100.00
hmac_test_sha512_vectors 427.000s 74331.821us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 325.589us 1 1 100.00
hmac_test_hmac384_vectors 11.000s 614.522us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 762.537us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 15.000s 1562.733us 1 1 100.00
hmac_long_msg 21.000s 4938.023us 1 1 100.00
hmac_back_pressure 48.000s 4974.443us 1 1 100.00
hmac_datapath_stress 25.000s 2989.683us 1 1 100.00
hmac_burst_wr 30.000s 30289.828us 1 1 100.00
hmac_error 35.000s 12880.330us 1 1 100.00
hmac_wipe_secret 69.000s 2307.685us 1 1 100.00
hmac_test_sha256_vectors 11.000s 239.910us 1 1 100.00
hmac_test_sha384_vectors 428.000s 17674.181us 1 1 100.00
hmac_test_sha512_vectors 427.000s 74331.821us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 325.589us 1 1 100.00
hmac_test_hmac384_vectors 11.000s 614.522us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 762.537us 1 1 100.00
hmac_stress_all 424.000s 87774.464us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 424.000s 87774.464us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 51.546us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 54.114us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 116.107us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 116.107us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 92.824us 1 1 100.00
hmac_csr_rw 2.000s 137.675us 1 1 100.00
hmac_csr_aliasing 3.000s 56.178us 1 1 100.00
hmac_same_csr_outstanding 2.000s 94.402us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 92.824us 1 1 100.00
hmac_csr_rw 2.000s 137.675us 1 1 100.00
hmac_csr_aliasing 3.000s 56.178us 1 1 100.00
hmac_same_csr_outstanding 2.000s 94.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 54.298us 1 1 100.00
hmac_tl_intg_err 3.000s 353.631us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.000s 353.631us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 15.000s 1562.733us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 147.117us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 107.000s 16194.583us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 517.519us 1 1 100.00