Simulation Results

Simulation Results: i2c

10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.82 %

code
85.66 %

assert
97.25 %

func
80.56 %

block
95.92 %

line
95.26 %

branch
92.68 %

toggle
72.68 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	52.000s	3675.444us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	19.000s	1986.840us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	83.530us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	24.941us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.000s	2331.836us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.000s	62.782us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	29.324us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	24.941us	1	1	100.00
	i2c_csr_aliasing	1.000s	62.782us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.000s	16.810us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	1047.000s	600000.000us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	159.000s	1282.857us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	18.006us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	2290.000s	11170.093us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1123.000s	2524.520us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	260.598us	1	1	100.00
	i2c_host_fifo_fmt_empty	39.000s	1429.736us	1	1	100.00
	i2c_host_fifo_reset_rx	3.000s	128.799us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	1272.000s	5358.336us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	15.000s	713.960us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	2.000s	277.744us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	5.000s	807.993us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	6.000s	1775.088us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	24.000s	6127.750us	1	1	100.00
	i2c_target_intr_smoke	5.000s	2967.781us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	187.257us	1	1	100.00
	i2c_target_fifo_reset_tx	2.000s	235.501us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	10.000s	11761.802us	1	1	100.00
	i2c_target_stress_rd	24.000s	6127.750us	1	1	100.00
	i2c_target_intr_stress_wr	699.000s	9835.125us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	7.000s	6254.154us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	5.000s	1889.786us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	5.000s	5264.646us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	30.000s	10145.927us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.000s	7310.529us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	605.361us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	159.000s	1282.857us	1	1	100.00
	i2c_host_perf_precise	7.000s	1171.824us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	15.000s	713.960us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.000s	136.410us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	3.000s	1916.445us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	887.721us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	2235.385us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	6.000s	6151.929us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	5.000s	1071.630us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	27.026us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	20.453us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	178.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	178.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	83.530us	1	1	100.00
	i2c_csr_rw	1.000s	24.941us	1	1	100.00
	i2c_csr_aliasing	1.000s	62.782us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	120.081us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	83.530us	1	1	100.00
	i2c_csr_rw	1.000s	24.941us	1	1	100.00
	i2c_csr_aliasing	1.000s	62.782us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	120.081us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	3.000s	80.704us	1	1	100.00
	i2c_sec_cm	2.000s	71.638us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	3.000s	80.704us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	30.000s	4581.602us	1
target_error_intr				1
	i2c_target_unexp_stop	1.000s	230.420us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	9.000s	1491.130us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	81533124579495757628308499111569080865933200489585444626692687337109455691210	126	UVM_INFO @ 4581602198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	113600792187036757597359107814577054893609606789682085722463567102440906031756	94	UVM_INFO @ 1491130144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_host_error_intr	106810418604418899123405490462969565123459332644220837684177656131420545347770	89	UVM_INFO @ 16810353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	i2c_host_stress_all	24381432315800735340928721281190164929915430845834068321196855533119047448931	116	UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	51016655922169464892390931106499526101368882786987485951722452168070071340159	93	UVM_INFO @ 807992638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	47750421777933559843831429046797221977009340360072891310363554070028825444555	87	UVM_INFO @ 230419830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	i2c_target_stress_all	105920754378875502160498918967582590259021903505622808747018800681035476683811	None
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	4953562282296611086072465124620642088157999651794186522819822664164754916081	88	UVM_INFO @ 10145926935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---