Simulation Results: lc_ctrl/volatile_unlock_disabled

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.67 %
  • code
  • 92.80 %
  • assert
  • 96.83 %
  • func
  • 88.39 %
  • block
  • 96.61 %
  • line
  • 97.29 %
  • branch
  • 91.38 %
  • toggle
  • 87.29 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 128.037us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 57.639us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 42.701us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 87.993us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 61.182us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 48.678us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 42.701us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 61.182us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 190.915us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 963.589us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 13.842us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 318.011us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.000s 364.072us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 1815.650us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.000s 364.072us 1 1 100.00
lc_ctrl_prog_failure 3.000s 318.011us 1 1 100.00
lc_ctrl_errors 5.000s 1815.650us 1 1 100.00
lc_ctrl_security_escalation 5.000s 397.462us 1 1 100.00
lc_ctrl_jtag_state_failure 17.000s 10153.719us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 1129.886us 1 1 100.00
lc_ctrl_jtag_errors 11.000s 3003.200us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 373.812us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 658.877us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 1129.886us 1 1 100.00
lc_ctrl_jtag_errors 11.000s 3003.200us 1 1 100.00
lc_ctrl_jtag_access 4.000s 363.168us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.000s 3388.728us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 217.221us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 80.287us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.000s 4640.310us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.000s 477.522us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 56.297us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 97.285us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 422.690us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.000s 318.435us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 39.608us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 15.000s 1371.761us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 45.067us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 323.808us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 323.808us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 57.639us 1 1 100.00
lc_ctrl_csr_rw 1.000s 42.701us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 61.182us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 75.236us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 57.639us 1 1 100.00
lc_ctrl_csr_rw 1.000s 42.701us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 61.182us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 75.236us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 495.413us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 47.298us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 47.298us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 963.589us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 364.072us 1 1 100.00
lc_ctrl_sec_cm 3.000s 495.413us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 364.072us 1 1 100.00
lc_ctrl_sec_cm 3.000s 495.413us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 364.072us 1 1 100.00
lc_ctrl_sec_cm 3.000s 495.413us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 364.072us 1 1 100.00
lc_ctrl_sec_cm 3.000s 495.413us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 364.072us 1 1 100.00
lc_ctrl_sec_cm 3.000s 495.413us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 364.072us 1 1 100.00
lc_ctrl_sec_cm 3.000s 495.413us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 364.072us 1 1 100.00
lc_ctrl_sec_cm 3.000s 495.413us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.000s 364.072us 1 1 100.00
lc_ctrl_sec_cm 3.000s 495.413us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 397.462us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 190.915us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 658.877us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 226.139us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 226.139us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 2382.270us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 1052.536us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 1052.536us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 34.000s 4599.876us 1 1 100.00