Simulation Results: lc_ctrl/volatile_unlock_enabled

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.81 %
  • code
  • 93.01 %
  • assert
  • 95.97 %
  • func
  • 86.45 %
  • block
  • 97.11 %
  • line
  • 97.69 %
  • branch
  • 92.68 %
  • toggle
  • 86.44 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 49.038us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 74.238us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 15.652us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 125.481us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 95.980us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 90.316us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 15.652us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 95.980us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 83.530us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 394.976us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 40.612us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 446.309us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 331.620us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 1948.741us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 331.620us 1 1 100.00
lc_ctrl_prog_failure 2.000s 446.309us 1 1 100.00
lc_ctrl_errors 5.000s 1948.741us 1 1 100.00
lc_ctrl_security_escalation 3.000s 792.432us 1 1 100.00
lc_ctrl_jtag_state_failure 11.000s 1084.567us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 333.844us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 16181.273us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.000s 69.946us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 3510.539us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 333.844us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 16181.273us 1 1 100.00
lc_ctrl_jtag_access 5.000s 3038.397us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.000s 1159.296us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 1191.004us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 50.836us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.000s 387.702us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 435.892us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 201.838us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 428.972us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 90.337us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 2643.868us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 28.409us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 69.000s 11683.102us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 76.880us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 44.917us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 44.917us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 74.238us 1 1 100.00
lc_ctrl_csr_rw 2.000s 15.652us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 95.980us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 178.491us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 74.238us 1 1 100.00
lc_ctrl_csr_rw 2.000s 15.652us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 95.980us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 178.491us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 242.860us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 640.479us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 640.479us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 394.976us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 331.620us 1 1 100.00
lc_ctrl_sec_cm 3.000s 242.860us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 331.620us 1 1 100.00
lc_ctrl_sec_cm 3.000s 242.860us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 331.620us 1 1 100.00
lc_ctrl_sec_cm 3.000s 242.860us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 331.620us 1 1 100.00
lc_ctrl_sec_cm 3.000s 242.860us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 331.620us 1 1 100.00
lc_ctrl_sec_cm 3.000s 242.860us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 331.620us 1 1 100.00
lc_ctrl_sec_cm 3.000s 242.860us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 331.620us 1 1 100.00
lc_ctrl_sec_cm 3.000s 242.860us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 331.620us 1 1 100.00
lc_ctrl_sec_cm 3.000s 242.860us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.000s 792.432us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 83.530us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 3510.539us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 867.246us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 867.246us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 2945.056us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 626.304us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 626.304us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 22.000s 26312.247us 1 1 100.00