Simulation Results: mbx

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.17 %
  • code
  • 85.98 %
  • assert
  • 96.96 %
  • func
  • 72.57 %
  • block
  • 94.47 %
  • line
  • 94.44 %
  • branch
  • 85.05 %
  • toggle
  • 78.44 %
Validation stages
V1
83.33%
V2
63.64%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 29.000s 2470.247us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 95.697us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 43.687us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 264.042us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 256.421us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 2.000s 38.892us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 43.687us 1 1 100.00
mbx_csr_aliasing 2.000s 256.421us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 8.000s 1711.207us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 3.000s 1024.550us 0 1 0.00
mbx_imbx_oob 0 1 0.00
mbx_imbx_oob 8.000s 992.020us 0 1 0.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 14.000s 1155.631us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 16.390us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 2.000s 90.683us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 2.000s 6.958us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 2.000s 6.958us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 95.697us 1 1 100.00
mbx_csr_rw 1.000s 43.687us 1 1 100.00
mbx_csr_aliasing 2.000s 256.421us 1 1 100.00
mbx_same_csr_outstanding 1.000s 17.179us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 95.697us 1 1 100.00
mbx_csr_rw 1.000s 43.687us 1 1 100.00
mbx_csr_aliasing 2.000s 256.421us 1 1 100.00
mbx_same_csr_outstanding 1.000s 17.179us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 108.155us 1 1 100.00
mbx_sec_cm 1.000s 33.808us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 2 test runs
mbx_stress_zero_delays 91303643234335254814456028763675660733145477604497336866915802313762018949514 413
UVM_INFO @ 1024549995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_imbx_oob 30547782974201711981736028541150167778175330452198560437646761851833365176927 114
UVM_INFO @ 992019625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:622) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 96270802494347797484875412552044048388229920463400334368799572580755206279070 85
TL item was: req: (cip_tl_seq_item@18677) { a_addr: 'h61d13774 a_data: 'h5d21dfb a_mask: 'h4 a_size: 'h2 a_param: 'h0 a_source: 'hb6 a_opcode: 'h1 a_user: 'h25f6a d_param: 'h0 d_source: 'hb6 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 6957816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 15071507562500358737778730064279476499407947393165543424551403401203751945451 86
TL item was: req: (cip_tl_seq_item@22531) { a_addr: 'h1be270b0 a_data: 'h47876a25 a_mask: 'h1 a_size: 'h0 a_param: 'h0 a_source: 'h91 a_opcode: 'h0 a_user: 'h255a1 d_param: 'h0 d_source: 'h91 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 38892265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 1 test run
mbx_stress 11231103579477927423166983745938683551718784084712510656478497755662157743124 255
UVM_INFO @ 1711207173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---