Simulation Results: otbn

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.04 %
  • code
  • 85.77 %
  • assert
  • 89.90 %
  • func
  • 97.46 %
  • block
  • 99.26 %
  • line
  • 99.47 %
  • branch
  • 94.61 %
  • toggle
  • 84.19 %
  • FSM
  • 64.79 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 13.000s 192.897us 1 1 100.00
otbn_smoke_vectorized 7.000s 33.373us 1 1 100.00
single_binary 1 1 100.00
otbn_single 11.000s 244.137us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 53.726us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 25.111us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 7.000s 49.259us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 55.550us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 137.334us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 25.111us 1 1 100.00
otbn_csr_aliasing 4.000s 55.550us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 50.000s 3108.797us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 30.000s 574.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 33.000s 110.977us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 66.000s 277.320us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 35.000s 568.474us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 31.000s 170.719us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 8.000s 25.140us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 8.000s 44.152us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 51.994us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 25.621us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 26.246us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 227.230us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 227.230us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 53.726us 1 1 100.00
otbn_csr_rw 3.000s 25.111us 1 1 100.00
otbn_csr_aliasing 4.000s 55.550us 1 1 100.00
otbn_same_csr_outstanding 6.000s 29.667us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 53.726us 1 1 100.00
otbn_csr_rw 3.000s 25.111us 1 1 100.00
otbn_csr_aliasing 4.000s 55.550us 1 1 100.00
otbn_same_csr_outstanding 6.000s 29.667us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 9.000s 18.938us 1 1 100.00
otbn_dmem_err 7.000s 154.527us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 10.000s 58.475us 1 1 100.00
otbn_controller_ispr_rdata_err 9.000s 75.275us 1 1 100.00
otbn_mac_bignum_acc_err 11.000s 60.766us 1 1 100.00
otbn_urnd_err 6.000s 30.977us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 6.000s 10.234us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 41.763us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 8.000s 16.246us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 187.000s 3316.287us 1 1 100.00
otbn_tl_intg_err 15.000s 149.188us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 27.000s 404.494us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 187.000s 3316.287us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 187.000s 3316.287us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 13.000s 192.897us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 7.000s 154.527us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 9.000s 18.938us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 15.000s 149.188us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 25.140us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 18.938us 1 1 100.00
otbn_dmem_err 7.000s 154.527us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 44.152us 1 1 100.00
otbn_illegal_mem_acc 6.000s 10.234us 1 1 100.00
otbn_sec_cm 187.000s 3316.287us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 187.000s 3316.287us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 11.000s 244.137us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 18.938us 1 1 100.00
otbn_dmem_err 7.000s 154.527us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 44.152us 1 1 100.00
otbn_illegal_mem_acc 6.000s 10.234us 1 1 100.00
otbn_sec_cm 187.000s 3316.287us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 187.000s 3316.287us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 25.140us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 18.938us 1 1 100.00
otbn_dmem_err 7.000s 154.527us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 44.152us 1 1 100.00
otbn_illegal_mem_acc 6.000s 10.234us 1 1 100.00
otbn_sec_cm 187.000s 3316.287us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 187.000s 3316.287us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 11.000s 244.137us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 11.000s 164.389us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 15.000s 46.595us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 30.000s 310.753us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 30.000s 310.753us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 14.000s 117.154us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 187.000s 3316.287us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 187.000s 3316.287us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 12.000s 230.377us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 187.000s 3316.287us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 187.000s 3316.287us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 12.000s 25.199us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 12.000s 25.199us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 12.000s 127.945us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 244.137us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 244.137us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 11.000s 244.137us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 35.000s 568.474us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 11.000s 244.137us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 11.000s 244.137us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 6.000s 25.386us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 11.000s 244.137us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 187.000s 3316.287us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 4.000s 6.521us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_base_vseq.sv:349) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 87435321907318627463769584825381152664669884575759579431828949393854283296420 144
UVM_INFO @ 6521150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_urnd_err 108622017698166407255361307201308545338000656699046485640592669536925843816759 112
UVM_ERROR @ 30977036 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 30977036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---