Simulation Results: otp_ctrl

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.20 %
  • code
  • 71.44 %
  • assert
  • 93.57 %
  • func
  • 51.59 %
  • line
  • 87.41 %
  • branch
  • 83.84 %
  • cond
  • 85.51 %
  • toggle
  • 64.83 %
  • FSM
  • 35.63 %
Validation stages
V1
100.00%
V2
70.00%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.630s 209.761us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 5.480s 463.304us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.690s 246.945us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.010s 95.352us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 8.800s 2439.831us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 12.000s 7020.827us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.060s 161.088us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.010s 95.352us 1 1 100.00
otp_ctrl_csr_aliasing 12.000s 7020.827us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.460s 64.800us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.390s 137.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 119.200s 7530.039us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 2.650s 99.109us 0 1 0.00
partition_check 2 2 100.00
otp_ctrl_background_chks 8.070s 1621.429us 1 1 100.00
otp_ctrl_check_fail 12.390s 1828.295us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.680s 573.984us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 8.260s 1248.187us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 9.930s 837.008us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 5.700s 268.111us 1 1 100.00
otp_ctrl_parallel_lc_esc 54.360s 26332.756us 1 1 100.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 4.040s 677.026us 0 1 0.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 20.290s 1691.251us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 15.890s 1832.100us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 2.410s 286.955us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.480s 117.786us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.710s 97.886us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.290s 541.255us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.290s 541.255us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.690s 246.945us 1 1 100.00
otp_ctrl_csr_rw 2.010s 95.352us 1 1 100.00
otp_ctrl_csr_aliasing 12.000s 7020.827us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.150s 358.923us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.690s 246.945us 1 1 100.00
otp_ctrl_csr_rw 2.010s 95.352us 1 1 100.00
otp_ctrl_csr_aliasing 12.000s 7020.827us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.150s 358.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
otp_ctrl_tl_intg_err 12.670s 827.517us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 12.670s 827.517us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 5.480s 463.304us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 5.480s 463.304us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 54.360s 26332.756us 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 54.360s 26332.756us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 54.360s 26332.756us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 54.360s 26332.756us 1 1 100.00
otp_ctrl_macro_errs 20.290s 1691.251us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 54.360s 26332.756us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 54.360s 26332.756us 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 54.360s 26332.756us 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 54.360s 26332.756us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 54.360s 26332.756us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 54.360s 26332.756us 1 1 100.00
otp_ctrl_macro_errs 20.290s 1691.251us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 54.360s 26332.756us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 54.360s 26332.756us 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 2.650s 99.109us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 12.390s 1828.295us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 8.260s 1248.187us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 8.260s 1248.187us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 8.260s 1248.187us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 8.260s 1248.187us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 8.260s 1248.187us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 5.480s 463.304us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 8.260s 1248.187us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 5.480s 463.304us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 300.130s 71053.824us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.680s 573.984us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 5.480s 463.304us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 5.480s 463.304us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 20.290s 1691.251us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 69.850s 68874.039us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 8.360s 1012.531us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_partition_walk 39387328495533776696333948144587817194876078971465347824834500734102170053269 160055
UVM_INFO @ 7530039347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 40829176782052529687709111686909152815637307479139147559472964907893404720897 1971
UVM_INFO @ 99108789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:677) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 2 test runs
otp_ctrl_dai_errs 100139143869056691487527145257380292759583569865273888711469149350310183646072 2252
UVM_INFO @ 677025833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 27809345274342248546923013304247563594566960890440100081602290531277846949129 9879
UVM_INFO @ 1832100058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 2 test runs
otp_ctrl_parallel_key_req 12495890816676039483162272969720497488053006672173420655383344308062062331230 7314
UVM_INFO @ 837007741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 36242605711013511764565316194104598051934764884494251271660264399725602511508 607
UVM_INFO @ 286955353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 39102710183476735544584085293109343739241679197345070735997665302255813346789 89
UVM_INFO @ 68874039277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all_with_rand_reset 54020689995595284689729635596618399964557206438792313444160320162327065727547 1343
UVM_INFO @ 1012531089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---