Simulation Results: rstmgr

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.23 %
  • code
  • 99.22 %
  • assert
  • 98.17 %
  • func
  • 97.29 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.52 %
  • toggle
  • 99.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.280s 67.032us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.350s 92.843us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.970s 37.162us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.630s 122.270us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.240s 44.634us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.430s 101.357us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.970s 37.162us 1 1 100.00
rstmgr_csr_aliasing 1.240s 44.634us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.490s 150.016us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.350s 37.062us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.070s 90.820us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.460s 745.121us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.460s 745.121us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.460s 745.121us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.460s 745.121us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 15.830s 2303.988us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.020s 40.383us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.820s 82.242us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.820s 82.242us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.350s 92.843us 1 1 100.00
rstmgr_csr_rw 0.970s 37.162us 1 1 100.00
rstmgr_csr_aliasing 1.240s 44.634us 1 1 100.00
rstmgr_same_csr_outstanding 1.070s 40.352us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.350s 92.843us 1 1 100.00
rstmgr_csr_rw 0.970s 37.162us 1 1 100.00
rstmgr_csr_aliasing 1.240s 44.634us 1 1 100.00
rstmgr_same_csr_outstanding 1.070s 40.352us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 23.000s 4524.802us 1 1 100.00
rstmgr_tl_intg_err 2.440s 328.691us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 23.000s 4524.802us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 23.000s 4524.802us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.440s 328.691us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.000s 58.405us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.550s 424.630us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.940s 292.557us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 23.000s 4524.802us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.970s 37.162us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.970s 37.162us 1 1 100.00