Simulation Results

Simulation Results: rv_dm/use_dmi_interface

10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
89.82 %

code
81.51 %

assert
96.82 %

func
91.13 %

block
92.57 %

line
93.00 %

branch
79.82 %

toggle
72.87 %

FSM
80.36 %

Validation stages

V1		96.30%
V2		73.91%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	34.000s	2688.553us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	30.000s	706.478us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	31.000s	313.424us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	46.000s	42916.136us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	31.000s	543.311us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	56.000s	23038.169us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	33.000s	2636.928us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	70.000s	34069.099us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	50.000s	52559.994us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	36.000s	178.204us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	30.000s	488.689us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	32.000s	878.108us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	34.000s	124.759us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	34.000s	100.248us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	34.000s	1738.353us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	30.000s	296.399us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	34.000s	178.536us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	36.000s	178.204us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	32.000s	209.489us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	32.000s	443.651us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	32.000s	878.108us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	32.000s	100.058us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	31.000s	163.083us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	34.000s	1521.335us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	54.000s	15789.435us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	65.000s	4447.752us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	30.000s	66.924us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	65.000s	4447.752us	1	1	100.00
	rv_dm_csr_rw	34.000s	1521.335us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	30.000s	81.047us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	36.000s	31.325us	1	1	100.00

17/23 passed

73.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	34.000s	2688.553us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	31.000s	286.432us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	30.000s	283.059us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	37.000s	167.973us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	33.000s	935.476us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	33.000s	1587.962us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	30.000s	56.434us	0	1	0.00
bad_sba				1	1	100.00
	rv_dm_bad_sba_tl_access	33.000s	3120.276us	1	1	100.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	30.000s	984.897us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	30.000s	192.107us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	32.000s	1008.513us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	30.000s	298.868us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	34.000s	257.462us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	49.000s	11553.829us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	53.000s	1679.046us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	31.000s	57.592us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	33.000s	3011.444us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	30.000s	65.024us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	33.000s	193.108us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	33.000s	193.108us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	65.000s	4447.752us	1	1	100.00
	rv_dm_csr_hw_reset	31.000s	163.083us	1	1	100.00
	rv_dm_csr_rw	34.000s	1521.335us	1	1	100.00
	rv_dm_same_csr_outstanding	34.000s	666.865us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	65.000s	4447.752us	1	1	100.00
	rv_dm_csr_hw_reset	31.000s	163.083us	1	1	100.00
	rv_dm_csr_rw	34.000s	1521.335us	1	1	100.00
	rv_dm_same_csr_outstanding	34.000s	666.865us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	33.000s	2636.727us	1	1	100.00
	rv_dm_tl_intg_err	36.000s	3409.215us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	36.000s	3409.215us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	32.000s	1008.513us	1	1	100.00
	rv_dm_debug_disabled	30.000s	73.864us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	32.000s	1008.513us	1	1	100.00
	rv_dm_debug_disabled	30.000s	73.864us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	34.000s	2688.553us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	30.000s	193.294us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	50.030us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	50.030us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	30.000s	193.294us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	36.000s	2656.134us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	146.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	73367416934488810072048256748043886636999099739453911957563588318547392711927	107	UVM_INFO @ 56433855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	80512286635733437537212996241090051727444198374230298540008566792755233731785	107	UVM_INFO @ 984896822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				2 test runs
	rv_dm_mem_tl_access_resuming	41894459424917941623082020402105057760154653432550663575753102395318576078118	87	UVM_INFO @ 124759327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	61604753548931860797798761515144557879107600618963999701066892953784122463102	91	UVM_INFO @ 3011443526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				1 test run
	rv_dm_sba_tl_access	97656248970174151402632156185340993286854520548782336075120577489495878118960	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23865
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	95227197153837523839193196541011886606575518016832730739947228161575107605929	87	UVM_INFO @ 257461757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	21937512512327200506110727715971055938223161392647657749827724126921641936885	87	UVM_INFO @ 192107154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	2600750357975982082562447570903150185852036463195728397099481358441374334573	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done)				1 test run
	rv_dm_stress_all_with_rand_reset	27706544917691524007231617124439595784374489873311149673063803811438286286814	96	UVM_INFO @ 2656133802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---