Simulation Results: rv_timer

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.18 %
  • code
  • 90.45 %
  • assert
  • 98.10 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 119.521us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 13.235us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 39.883us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 371.750us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 111.805us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 19.369us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 39.883us 1 1 100.00
rv_timer_csr_aliasing 1.000s 111.805us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.000s 65.086us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 3846.349us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 4.000s 3950.482us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 4.000s 3950.482us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.000s 3096.898us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 14.079us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 17.589us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 79.584us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 79.584us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 13.235us 1 1 100.00
rv_timer_csr_rw 1.000s 39.883us 1 1 100.00
rv_timer_csr_aliasing 1.000s 111.805us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 20.826us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 13.235us 1 1 100.00
rv_timer_csr_rw 1.000s 39.883us 1 1 100.00
rv_timer_csr_aliasing 1.000s 111.805us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 20.826us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 2.000s 177.309us 1 1 100.00
rv_timer_tl_intg_err 1.000s 309.478us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 309.478us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 1.000s 35.265us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 3.000s 506.123us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 15.000s 4102.163us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 102220795247305419576903261139287016014813051347352412486058821833611847973626 84
UVM_INFO @ 506122780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_random_reset 61953712398400343408811123664154278543298874098923466666154237863870367147977 85
UVM_INFO @ 65085966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 1 test run
rv_timer_stress_all_with_rand_reset 37368390258757277776047942053895290883517944779110962947474845203958641397986 195
UVM_INFO @ 4102162663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---