Simulation Results: spi_host

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.97 %
  • code
  • 91.14 %
  • assert
  • 95.27 %
  • func
  • 89.50 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 92.95 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 49.000s 9735.123us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 59.932us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 18.547us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 150.966us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 94.494us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 23.393us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 18.547us 1 1 100.00
spi_host_csr_aliasing 2.000s 94.494us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 14.361us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 23.590us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 63.779us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 197.918us 1 1 100.00
spi_host_error_cmd 1.000s 52.367us 1 1 100.00
spi_host_event 19.000s 15793.836us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 258.113us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 258.113us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 258.113us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 19.000s 1925.237us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 16.000s 936.020us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 49.663us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 258.113us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 258.113us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 49.000s 9735.123us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 49.000s 9735.123us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 1.000s 36.810us 1 1 100.00
spien 1 1 100.00
spi_host_spien 7.000s 693.043us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 74.000s 36414.926us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 62.478us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 197.918us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 25.725us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 17.223us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 77.807us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 77.807us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 59.932us 1 1 100.00
spi_host_csr_rw 1.000s 18.547us 1 1 100.00
spi_host_csr_aliasing 2.000s 94.494us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 25.258us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 59.932us 1 1 100.00
spi_host_csr_rw 1.000s 18.547us 1 1 100.00
spi_host_csr_aliasing 2.000s 94.494us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 25.258us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 102.894us 1 1 100.00
spi_host_sec_cm 2.000s 68.343us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 102.894us 1 1 100.00