Simulation Results: sram_ctrl/main

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.80 %
  • code
  • 95.70 %
  • assert
  • 98.10 %
  • func
  • 93.60 %
  • block
  • 96.09 %
  • line
  • 96.82 %
  • branch
  • 94.16 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 676.766us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 26.268us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.996us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 189.199us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 18.639us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 6789.436us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 18.996us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 18.639us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 231.000s 26853.286us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 51.000s 36063.952us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 17.000s 8052.098us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 157.000s 8322.034us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 122.000s 8211.113us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 55.000s 45208.966us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.000s 1740.122us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 21.000s 18149.485us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 698.912us 1 1 100.00
sram_ctrl_partial_access_b2b 346.000s 51907.644us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 9533.591us 1 1 100.00
sram_ctrl_throughput_w_partial_write 3.000s 685.368us 1 1 100.00
sram_ctrl_throughput_w_readback 6.000s 2685.940us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 13.000s 2117.833us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 973.998us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 289.000s 20514.804us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 13.864us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 48.229us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 48.229us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 26.268us 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.996us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 18.639us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 14.683us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 26.268us 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.996us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 18.639us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 14.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.000s 23087.988us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 243.935us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 186.575us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 243.935us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 186.575us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 2117.833us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 2117.833us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.996us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 21.000s 18149.485us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 21.000s 18149.485us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 21.000s 18149.485us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.000s 1740.122us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 2667.832us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.000s 23087.988us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 2659.301us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 676.766us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 676.766us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 21.000s 18149.485us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 243.935us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.000s 1740.122us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 243.935us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 243.935us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 676.766us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 243.935us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 32.000s 1976.283us 1 1 100.00