Simulation Results: sram_ctrl/ret

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.53 %
  • code
  • 82.13 %
  • assert
  • 97.67 %
  • func
  • 94.80 %
  • block
  • 93.47 %
  • line
  • 94.53 %
  • branch
  • 89.01 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 127.735us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 16.083us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 67.550us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 442.744us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.658us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 27.983us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 67.550us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.658us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.000s 848.985us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 129.677us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 10.000s 391.016us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 179.000s 3574.443us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 8.000s 3069.666us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 7.000s 399.023us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 2.000s 235.642us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 7.000s 323.559us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 52.275us 1 1 100.00
sram_ctrl_partial_access_b2b 175.000s 29517.128us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 40.527us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 144.107us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 79.046us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 774.244us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 32.310us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 43.000s 30882.065us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 24.875us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 86.370us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 86.370us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.083us 1 1 100.00
sram_ctrl_csr_rw 2.000s 67.550us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.658us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 24.893us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.083us 1 1 100.00
sram_ctrl_csr_rw 2.000s 67.550us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.658us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 24.893us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 627.544us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 364.414us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 427.164us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 364.414us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 427.164us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 774.244us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 774.244us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 67.550us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 7.000s 323.559us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 323.559us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 323.559us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 2.000s 235.642us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 70.892us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 627.544us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 115.932us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 127.735us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 127.735us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 7.000s 323.559us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 364.414us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 2.000s 235.642us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 364.414us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 364.414us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 127.735us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 364.414us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 13.000s 2367.852us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 9149184110528323308200647543784697681390601304288612811712959351701194802115 94
UVM_INFO @ 27983036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---