Simulation Results

Simulation Results: uart

10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.80 %

code
92.73 %

assert
97.98 %

func
90.69 %

block
99.08 %

line
99.52 %

branch
98.34 %

toggle
73.08 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		95.45%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	3.000s	540.511us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	1.000s	23.537us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	2.000s	18.764us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	2.000s	149.608us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	1.000s	267.982us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	2.000s	17.054us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	2.000s	18.764us	1	1	100.00
	uart_csr_aliasing	1.000s	267.982us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	29.000s	91177.021us	1	1	100.00
parity				2	2	100.00
	uart_smoke	3.000s	540.511us	1	1	100.00
	uart_tx_rx	29.000s	91177.021us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	85.000s	79915.805us	1	1	100.00
	uart_rx_parity_err	27.000s	21974.322us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	29.000s	91177.021us	1	1	100.00
	uart_intr	85.000s	79915.805us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	157.000s	168468.653us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	83.000s	256552.250us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	37.000s	113444.412us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	85.000s	79915.805us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	85.000s	79915.805us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	85.000s	79915.805us	1	1	100.00
perf				1	1	100.00
	uart_perf	357.000s	17460.604us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	4.000s	2818.413us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	4.000s	2818.413us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	37.000s	46042.042us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	3.000s	3552.171us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	2.000s	627.330us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	10.000s	2433.237us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	326.000s	66683.749us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	356.000s	137279.430us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	1.000s	13.549us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	1.000s	18.406us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	2.000s	179.509us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	2.000s	179.509us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	1.000s	23.537us	1	1	100.00
	uart_csr_rw	2.000s	18.764us	1	1	100.00
	uart_csr_aliasing	1.000s	267.982us	1	1	100.00
	uart_same_csr_outstanding	2.000s	34.276us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	1.000s	23.537us	1	1	100.00
	uart_csr_rw	2.000s	18.764us	1	1	100.00
	uart_csr_aliasing	1.000s	267.982us	1	1	100.00
	uart_same_csr_outstanding	2.000s	34.276us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	1.000s	224.277us	1	1	100.00
	uart_tl_intg_err	2.000s	78.179us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	2.000s	78.179us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	45.000s	9878.872us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				1 test run
	uart_noise_filter	30416617110753260125068355962816483170840442385901458673373443719449083583022	88	UVM_ERROR @ 39961260808 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 39971604558 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 39972073308 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 39973885808 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0