Simulation Results: aes/gcm_unmasked

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.42 %
  • code
  • 91.09 %
  • assert
  • 97.75 %
  • func
  • 61.42 %
  • block
  • 90.74 %
  • line
  • 92.48 %
  • branch
  • 83.13 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 118.225us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 123.266us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 110.353us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 61.066us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 3512.272us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 274.983us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 220.840us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 61.066us 1 1 100.00
aes_csr_aliasing 3.000s 274.983us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 123.266us 1 1 100.00
aes_config_error 2.000s 80.326us 1 1 100.00
aes_stress 3.000s 177.113us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 123.266us 1 1 100.00
aes_config_error 2.000s 80.326us 1 1 100.00
aes_stress 3.000s 177.113us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 177.113us 1 1 100.00
aes_b2b 3.000s 96.641us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 177.113us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 123.266us 1 1 100.00
aes_config_error 2.000s 80.326us 1 1 100.00
aes_stress 3.000s 177.113us 1 1 100.00
aes_alert_reset 3.000s 101.961us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 54.489us 1 1 100.00
aes_config_error 2.000s 80.326us 1 1 100.00
aes_alert_reset 3.000s 101.961us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 179.744us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 513.072us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 101.961us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 177.113us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 177.113us 1 1 100.00
aes_sideload 2.000s 147.887us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 137.513us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10802.130s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 53.838us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 86.922us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 86.922us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 110.353us 1 1 100.00
aes_csr_rw 1.000s 61.066us 1 1 100.00
aes_csr_aliasing 3.000s 274.983us 1 1 100.00
aes_same_csr_outstanding 2.000s 94.167us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 110.353us 1 1 100.00
aes_csr_rw 1.000s 61.066us 1 1 100.00
aes_csr_aliasing 3.000s 274.983us 1 1 100.00
aes_same_csr_outstanding 2.000s 94.167us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 107.338us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 48.429us 1 1 100.00
aes_cipher_fi 2.000s 54.281us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 86.058us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 86.058us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 86.058us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 86.058us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 250.943us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 1033.068us 1 1 100.00
aes_tl_intg_err 1.000s 121.280us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 1.000s 121.280us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 101.961us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 86.058us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 86.058us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 123.266us 1 1 100.00
aes_stress 3.000s 177.113us 1 1 100.00
aes_alert_reset 3.000s 101.961us 1 1 100.00
aes_core_fi 2.000s 104.969us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 80.326us 1 1 100.00
aes_stress 3.000s 177.113us 1 1 100.00
aes_core_fi 2.000s 104.969us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 86.058us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 66.474us 1 1 100.00
aes_stress 3.000s 177.113us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 177.113us 1 1 100.00
aes_sideload 2.000s 147.887us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 66.474us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 66.474us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 66.474us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 66.474us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 66.474us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 177.113us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 177.113us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 48.429us 1 1 100.00
aes_cipher_fi 2.000s 54.281us 1 1 100.00
aes_ctr_fi 2.000s 90.814us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 48.429us 1 1 100.00
aes_cipher_fi 2.000s 54.281us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 54.281us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 48.429us 1 1 100.00
aes_ctr_fi 2.000s 90.814us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 48.429us 1 1 100.00
aes_cipher_fi 2.000s 54.281us 1 1 100.00
aes_ctr_fi 2.000s 90.814us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 101.961us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 48.429us 1 1 100.00
aes_cipher_fi 2.000s 54.281us 1 1 100.00
aes_ctr_fi 2.000s 90.814us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 48.429us 1 1 100.00
aes_cipher_fi 2.000s 54.281us 1 1 100.00
aes_ctr_fi 2.000s 90.814us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 48.429us 1 1 100.00
aes_ctr_fi 2.000s 90.814us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 48.429us 1 1 100.00
aes_cipher_fi 2.000s 54.281us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 31.358us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
aes_fi 30624914658775013172443253762036752778634280090345257888043216576108795730135 None
aes_stress_all 68189361032429249682526481793941226606220510814961801499207063587441346706846 None
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 115275237831341830611552093988682807060310575621929263960114140113812145319106 152
UVM_INFO @ 31357515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---