Simulation Results: clkmgr

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.57 %
  • code
  • 68.91 %
  • assert
  • 90.08 %
  • func
  • 70.73 %
  • line
  • 81.76 %
  • branch
  • 86.53 %
  • cond
  • 79.19 %
  • toggle
  • 97.08 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
69.23%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.040s 51.117us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.060s 61.403us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.900s 30.224us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 2.670s 153.066us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.820s 9.096us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.230s 72.995us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.900s 30.224us 1 1 100.00
clkmgr_csr_aliasing 0.820s 9.096us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.820s 30.165us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.720s 61.707us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.940s 40.050us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.040s 51.117us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 1.240s 54.341us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.680s 3.195us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 1.240s 54.341us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.730s 10.001us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.990s 29.617us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 7.590s 838.338us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 7.590s 838.338us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
clkmgr_csr_hw_reset 1.060s 61.403us 1 1 100.00
clkmgr_csr_rw 0.900s 30.224us 1 1 100.00
clkmgr_csr_aliasing 0.820s 9.096us 0 1 0.00
clkmgr_same_csr_outstanding 1.150s 23.436us 1 1 100.00
tl_d_partial_access 3 4 75.00
clkmgr_csr_hw_reset 1.060s 61.403us 1 1 100.00
clkmgr_csr_rw 0.900s 30.224us 1 1 100.00
clkmgr_csr_aliasing 0.820s 9.096us 0 1 0.00
clkmgr_same_csr_outstanding 1.150s 23.436us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 1.010s 20.872us 0 1 0.00
clkmgr_tl_intg_err 0.890s 9.376us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.140s 54.394us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.140s 54.394us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.140s 54.394us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.140s 54.394us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.860s 20.166us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.890s 9.376us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 1.240s 54.341us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.680s 3.195us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.140s 54.394us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.770s 17.575us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.900s 30.224us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.010s 20.872us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.900s 30.224us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.900s 30.224us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.010s 20.872us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.630s 2.260us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 2.350s 78.192us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency 67112846160759929708931399005845702586267590148125562810982896533328781667750 76
UVM_INFO @ 54341265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 47725252911091716800234125826454321433042094456321548773571586693190595717001 93
UVM_INFO @ 78191714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 32782240843967006622906976513746116228375925255617355690700026999269426420464 76
UVM_INFO @ 10001459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 3366458780993581698952416371011783160220578712334562313360251271729246919861 75
UVM_INFO @ 20165823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 33498527000531575346213458736297691553837305052423197660690097813445181883214 75
UVM_INFO @ 9096355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 2 test runs
clkmgr_tl_intg_err 1942469850109834837547526467979375059174524678087074508810473117923373124620 86
UVM_INFO @ 9376407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 104357691560440909635931291761905632455569510126468165377337124159770694154854 76
UVM_INFO @ 72994842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency_timeout 85603084860734658611578824383699034099019686671307242621111845678209316677169 77
UVM_INFO @ 3194880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 45785048957227390592026390869039405940500849553384076698678670766662297335236 74
UVM_INFO @ 2259777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 92932520496915884252856874995847743890600704825591221620135421256383626520252 95
UVM_INFO @ 20871667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 439474506540295570573429878264162061146575304944450148186868857092730272951 75
UVM_INFO @ 153066284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---