Simulation Results: csrng

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.62 %
  • code
  • 92.20 %
  • assert
  • 94.10 %
  • func
  • 76.55 %
  • block
  • 96.92 %
  • line
  • 97.69 %
  • branch
  • 92.43 %
  • toggle
  • 92.97 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 68.885us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 1.000s 36.807us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 31.019us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 8.000s 162.167us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 35.756us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 36.875us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 31.019us 1 1 100.00
csrng_csr_aliasing 2.000s 35.756us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 3.000s 58.419us 1 1 100.00
alerts 1 1 100.00
csrng_alert 18.000s 749.932us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 22.679us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 3.000s 72.164us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 3.000s 72.164us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 700.000s 31334.472us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 24.804us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 57.108us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 112.166us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 112.166us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 1.000s 36.807us 1 1 100.00
csrng_csr_rw 2.000s 31.019us 1 1 100.00
csrng_csr_aliasing 2.000s 35.756us 1 1 100.00
csrng_same_csr_outstanding 2.000s 32.158us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 1.000s 36.807us 1 1 100.00
csrng_csr_rw 2.000s 31.019us 1 1 100.00
csrng_csr_aliasing 2.000s 35.756us 1 1 100.00
csrng_same_csr_outstanding 2.000s 32.158us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 2.000s 42.391us 1 1 100.00
csrng_tl_intg_err 4.000s 97.227us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 1.000s 1.977us 0 1 0.00
csrng_csr_rw 2.000s 31.019us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 18.000s 749.932us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 700.000s 31334.472us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 3.000s 58.419us 1 1 100.00
csrng_err 2.000s 22.679us 1 1 100.00
csrng_sec_cm 2.000s 42.391us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 3.000s 58.419us 1 1 100.00
csrng_err 2.000s 22.679us 1 1 100.00
csrng_sec_cm 2.000s 42.391us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 3.000s 58.419us 1 1 100.00
csrng_err 2.000s 22.679us 1 1 100.00
csrng_sec_cm 2.000s 42.391us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 3.000s 58.419us 1 1 100.00
csrng_err 2.000s 22.679us 1 1 100.00
csrng_sec_cm 2.000s 42.391us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 3.000s 58.419us 1 1 100.00
csrng_err 2.000s 22.679us 1 1 100.00
csrng_sec_cm 2.000s 42.391us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 18.000s 749.932us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 3.000s 58.419us 1 1 100.00
csrng_err 2.000s 22.679us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 700.000s 31334.472us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 18.000s 749.932us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 97.227us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 3.000s 58.419us 1 1 100.00
csrng_err 2.000s 22.679us 1 1 100.00
csrng_sec_cm 2.000s 42.391us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 3.000s 58.419us 1 1 100.00
csrng_err 2.000s 22.679us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 3.000s 58.419us 1 1 100.00
csrng_err 2.000s 22.679us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 3.000s 58.419us 1 1 100.00
csrng_err 2.000s 22.679us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 3.000s 58.419us 1 1 100.00
csrng_err 2.000s 22.679us 1 1 100.00
csrng_sec_cm 2.000s 42.391us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 3.000s 58.419us 1 1 100.00
csrng_err 2.000s 22.679us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 37929258642718387150494360448187070279212817666387243996147187987253320229075 100
UVM_INFO @ 72163551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 1 test run
csrng_regwen 33637389992220617498181664388992815091790583436682020408947016505481776377465 99
UVM_INFO @ 1977116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 19166427285318953697032751817307041821208481134543708290145276132645090183757 None