Simulation Results: edn/edn0

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 79.08 %
  • code
  • 91.82 %
  • assert
  • 96.90 %
  • func
  • 48.53 %
  • block
  • 96.04 %
  • line
  • 98.10 %
  • branch
  • 91.30 %
  • toggle
  • 83.30 %
  • FSM
  • 94.57 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 51.445us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 46.661us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 13.701us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 6.000s 648.882us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 144.562us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 36.170us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 13.701us 1 1 100.00
edn_csr_aliasing 2.000s 144.562us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 112.638us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 112.638us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 112.638us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 22.090us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 53.152us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 20.206us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 12.821us 1 1 100.00
edn_disable_auto_req_mode 1.000s 26.856us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 7.000s 195.512us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 14.620us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 52.870us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 4.000s 233.695us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 4.000s 233.695us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 46.661us 1 1 100.00
edn_csr_rw 1.000s 13.701us 1 1 100.00
edn_csr_aliasing 2.000s 144.562us 1 1 100.00
edn_same_csr_outstanding 1.000s 37.919us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 46.661us 1 1 100.00
edn_csr_rw 1.000s 13.701us 1 1 100.00
edn_csr_aliasing 2.000s 144.562us 1 1 100.00
edn_same_csr_outstanding 1.000s 37.919us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.000s 303.791us 1 1 100.00
edn_tl_intg_err 2.000s 47.636us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 28.920us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 53.152us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 303.791us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 303.791us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 303.791us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 303.791us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 53.152us 1 1 100.00
edn_sec_cm 4.000s 303.791us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 53.152us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 47.636us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 38.000s 1626.055us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 62949121730622195281692436121154326885556008933001978603028466126960880607260 176
UVM_INFO @ 1626054695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---