Simulation Results: edn/edn1

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.67 %
  • code
  • 83.80 %
  • assert
  • 97.92 %
  • func
  • 81.30 %
  • line
  • 97.72 %
  • branch
  • 92.21 %
  • cond
  • 90.69 %
  • toggle
  • 95.19 %
  • FSM
  • 43.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.850s 64.522us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.990s 16.325us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.850s 18.016us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.320s 642.093us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.320s 25.802us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.270s 36.800us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.850s 18.016us 1 1 100.00
edn_csr_aliasing 1.320s 25.802us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.930s 22.395us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.930s 22.395us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.930s 22.395us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.910s 22.360us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.250s 81.426us 1 1 100.00
errs 1 1 100.00
edn_err 1.230s 21.761us 1 1 100.00
disable 2 2 100.00
edn_disable 0.820s 13.341us 1 1 100.00
edn_disable_auto_req_mode 1.080s 372.212us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.140s 463.652us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.720s 59.987us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.030s 17.557us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.300s 120.312us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.300s 120.312us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.990s 16.325us 1 1 100.00
edn_csr_rw 0.850s 18.016us 1 1 100.00
edn_csr_aliasing 1.320s 25.802us 1 1 100.00
edn_same_csr_outstanding 0.840s 70.698us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.990s 16.325us 1 1 100.00
edn_csr_rw 0.850s 18.016us 1 1 100.00
edn_csr_aliasing 1.320s 25.802us 1 1 100.00
edn_same_csr_outstanding 0.840s 70.698us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.120s 6261.869us 1 1 100.00
edn_tl_intg_err 2.360s 364.504us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 31.919us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.250s 81.426us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.120s 6261.869us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.120s 6261.869us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.120s 6261.869us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.120s 6261.869us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.250s 81.426us 1 1 100.00
edn_sec_cm 5.120s 6261.869us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.250s 81.426us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.360s 364.504us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 76.030s 20368.190us 1 1 100.00