Simulation Results: hmac

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.94 %
  • code
  • 96.00 %
  • assert
  • 96.96 %
  • func
  • 28.85 %
  • block
  • 97.51 %
  • line
  • 98.44 %
  • branch
  • 93.76 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 13.000s 2527.496us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 60.688us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 56.290us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 5.000s 1534.069us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.000s 184.114us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 118.696us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 56.290us 1 1 100.00
hmac_csr_aliasing 5.000s 184.114us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 33.000s 6397.153us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 59.000s 11096.278us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 212.000s 68549.134us 1 1 100.00
hmac_test_sha384_vectors 324.000s 12922.451us 1 1 100.00
hmac_test_sha512_vectors 24.000s 327.954us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 452.019us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 612.504us 1 1 100.00
hmac_test_hmac512_vectors 10.000s 349.872us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 12.000s 353.340us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 208.000s 25511.625us 1 1 100.00
error 1 1 100.00
hmac_error 80.000s 39723.778us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 109.000s 10829.157us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 13.000s 2527.496us 1 1 100.00
hmac_long_msg 33.000s 6397.153us 1 1 100.00
hmac_back_pressure 59.000s 11096.278us 1 1 100.00
hmac_datapath_stress 208.000s 25511.625us 1 1 100.00
hmac_burst_wr 12.000s 353.340us 1 1 100.00
hmac_stress_all 108.000s 3829.314us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 13.000s 2527.496us 1 1 100.00
hmac_long_msg 33.000s 6397.153us 1 1 100.00
hmac_back_pressure 59.000s 11096.278us 1 1 100.00
hmac_datapath_stress 208.000s 25511.625us 1 1 100.00
hmac_wipe_secret 109.000s 10829.157us 1 1 100.00
hmac_test_sha256_vectors 212.000s 68549.134us 1 1 100.00
hmac_test_sha384_vectors 324.000s 12922.451us 1 1 100.00
hmac_test_sha512_vectors 24.000s 327.954us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 452.019us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 612.504us 1 1 100.00
hmac_test_hmac512_vectors 10.000s 349.872us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 13.000s 2527.496us 1 1 100.00
hmac_long_msg 33.000s 6397.153us 1 1 100.00
hmac_back_pressure 59.000s 11096.278us 1 1 100.00
hmac_datapath_stress 208.000s 25511.625us 1 1 100.00
hmac_burst_wr 12.000s 353.340us 1 1 100.00
hmac_error 80.000s 39723.778us 1 1 100.00
hmac_wipe_secret 109.000s 10829.157us 1 1 100.00
hmac_test_sha256_vectors 212.000s 68549.134us 1 1 100.00
hmac_test_sha384_vectors 324.000s 12922.451us 1 1 100.00
hmac_test_sha512_vectors 24.000s 327.954us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 452.019us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 612.504us 1 1 100.00
hmac_test_hmac512_vectors 10.000s 349.872us 1 1 100.00
hmac_stress_all 108.000s 3829.314us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 108.000s 3829.314us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 12.778us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 47.831us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 300.585us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 300.585us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 60.688us 1 1 100.00
hmac_csr_rw 1.000s 56.290us 1 1 100.00
hmac_csr_aliasing 5.000s 184.114us 1 1 100.00
hmac_same_csr_outstanding 2.000s 169.118us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 60.688us 1 1 100.00
hmac_csr_rw 1.000s 56.290us 1 1 100.00
hmac_csr_aliasing 5.000s 184.114us 1 1 100.00
hmac_same_csr_outstanding 2.000s 169.118us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 234.058us 1 1 100.00
hmac_tl_intg_err 4.000s 480.561us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 4.000s 480.561us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 13.000s 2527.496us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.000s 156.536us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 39.000s 5649.929us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 53.559us 1 1 100.00