Simulation Results: i2c

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.38 %
  • code
  • 86.35 %
  • assert
  • 97.25 %
  • func
  • 81.55 %
  • block
  • 96.30 %
  • line
  • 95.65 %
  • branch
  • 93.39 %
  • toggle
  • 72.19 %
  • FSM
  • 84.17 %
Validation stages
V1
100.00%
V2
87.80%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 59.000s 2381.056us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 9.000s 3257.356us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 1.000s 21.295us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 2.000s 23.008us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 4.000s 341.190us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 3.000s 67.056us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.000s 91.380us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 2.000s 23.008us 1 1 100.00
i2c_csr_aliasing 3.000s 67.056us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 5.000s 1192.473us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 3600.000s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 84.000s 27854.435us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 1.000s 381.160us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 2660.000s 5992.214us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 1261.000s 8627.929us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 2.000s 81.705us 1 1 100.00
i2c_host_fifo_fmt_empty 49.000s 1897.341us 1 1 100.00
i2c_host_fifo_reset_rx 6.000s 244.598us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 1483.000s 35539.781us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 8.000s 5743.749us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 3.000s 577.894us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 3.000s 1348.679us 0 1 0.00
target_stress_all 0 1 0.00
i2c_target_stress_all 3600.000s 0.000us 0 1 0.00
target_maxperf 1 1 100.00
i2c_target_perf 6.000s 985.607us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 5.000s 412.769us 1 1 100.00
i2c_target_intr_smoke 8.000s 1584.511us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 3.000s 546.801us 1 1 100.00
i2c_target_fifo_reset_tx 3.000s 1021.335us 1 1 100.00
target_fifo_full 2 3 66.67
i2c_target_stress_wr 3600.000s 0.000us 0 1 0.00
i2c_target_stress_rd 5.000s 412.769us 1 1 100.00
i2c_target_intr_stress_wr 814.000s 18047.565us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 8.000s 5781.456us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 1953.000s 3862.706us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 4.000s 1682.173us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 4.000s 319.494us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 5.000s 1788.723us 1 1 100.00
i2c_target_fifo_watermarks_tx 2.000s 155.080us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 84.000s 27854.435us 1 1 100.00
i2c_host_perf_precise 5.000s 638.827us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 8.000s 5743.749us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 3.000s 190.949us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 4.000s 547.662us 1 1 100.00
i2c_target_nack_acqfull_addr 4.000s 1947.436us 1 1 100.00
i2c_target_nack_txstretch 3.000s 130.700us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 8.000s 952.842us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 3.000s 1198.184us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 2.000s 44.304us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 1.000s 50.583us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 3.000s 205.647us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 3.000s 205.647us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 1.000s 21.295us 1 1 100.00
i2c_csr_rw 2.000s 23.008us 1 1 100.00
i2c_csr_aliasing 3.000s 67.056us 1 1 100.00
i2c_same_csr_outstanding 2.000s 75.605us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 1.000s 21.295us 1 1 100.00
i2c_csr_rw 2.000s 23.008us 1 1 100.00
i2c_csr_aliasing 3.000s 67.056us 1 1 100.00
i2c_same_csr_outstanding 2.000s 75.605us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 3.000s 270.590us 1 1 100.00
i2c_sec_cm 2.000s 139.713us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 3.000s 270.590us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 4.000s 233.355us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 2.000s 425.207us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 3.000s 194.508us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 3 test runs
i2c_host_stress_all 70993040858851127228690499553241164157490762337734777099284538777628778520093 None
i2c_target_stress_wr 11271493913450239342438782914970905843883764438199274401891944713765205834971 None
i2c_target_stress_all 5534796943174303834160538049958048239947297663193294990401492144174527346386 None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 2 test runs
i2c_host_error_intr 16604359496277477801629887733781951816383805137591409242952571159518639370402 113
UVM_INFO @ 1192472888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 11864025389923897862306110410649347893378010181627161457853453600845539547359 115
UVM_INFO @ 194508114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 98326059682184253709869080337835186297568351919717186183175939204310193857040 93
UVM_INFO @ 1348678771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 25963928310404543723342234405929368413328437223877196347783620097511132349675 87
UVM_INFO @ 425207018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 73588109268280488088361392307681159972619990387331212066668289939093839329862 95
UVM_INFO @ 233354614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---