Simulation Results: lc_ctrl/volatile_unlock_disabled

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.33 %
  • code
  • 92.52 %
  • assert
  • 95.97 %
  • func
  • 85.48 %
  • block
  • 96.66 %
  • line
  • 97.35 %
  • branch
  • 91.49 %
  • toggle
  • 86.02 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 384.907us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 73.464us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 19.128us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 210.082us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 40.976us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 83.729us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 19.128us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 40.976us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 811.737us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 412.010us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 13.644us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 465.679us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 3.000s 214.547us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.000s 237.546us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 3.000s 214.547us 1 1 100.00
lc_ctrl_prog_failure 3.000s 465.679us 1 1 100.00
lc_ctrl_errors 4.000s 237.546us 1 1 100.00
lc_ctrl_security_escalation 4.000s 1079.096us 1 1 100.00
lc_ctrl_jtag_state_failure 17.000s 9693.293us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.000s 90.443us 1 1 100.00
lc_ctrl_jtag_errors 18.000s 1848.489us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.000s 198.041us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.000s 840.259us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.000s 90.443us 1 1 100.00
lc_ctrl_jtag_errors 18.000s 1848.489us 1 1 100.00
lc_ctrl_jtag_access 5.000s 463.904us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.000s 6384.753us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 625.136us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 164.584us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.000s 1064.437us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 8.000s 2958.342us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 66.168us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 1942.034us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 27.640us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.000s 993.817us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 84.184us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 124.000s 8748.129us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 24.138us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 69.586us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 69.586us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 73.464us 1 1 100.00
lc_ctrl_csr_rw 2.000s 19.128us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 40.976us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 27.518us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 73.464us 1 1 100.00
lc_ctrl_csr_rw 2.000s 19.128us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 40.976us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 27.518us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 591.583us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 149.511us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 149.511us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 412.010us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 214.547us 1 1 100.00
lc_ctrl_sec_cm 4.000s 591.583us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 214.547us 1 1 100.00
lc_ctrl_sec_cm 4.000s 591.583us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 3.000s 214.547us 1 1 100.00
lc_ctrl_sec_cm 4.000s 591.583us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 3.000s 214.547us 1 1 100.00
lc_ctrl_sec_cm 4.000s 591.583us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 214.547us 1 1 100.00
lc_ctrl_sec_cm 4.000s 591.583us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 214.547us 1 1 100.00
lc_ctrl_sec_cm 4.000s 591.583us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 214.547us 1 1 100.00
lc_ctrl_sec_cm 4.000s 591.583us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 3.000s 214.547us 1 1 100.00
lc_ctrl_sec_cm 4.000s 591.583us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 1079.096us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 811.737us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.000s 840.259us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 557.480us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 557.480us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.000s 512.055us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 497.094us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 497.094us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 6.000s 697.729us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 106917529225408078725953179602813638889074553204249386773491334704036928016940 1483
UVM_INFO @ 697729338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---