Simulation Results: mbx

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.38 %
  • code
  • 89.18 %
  • assert
  • 96.96 %
  • func
  • 78.99 %
  • block
  • 96.88 %
  • line
  • 96.71 %
  • branch
  • 91.89 %
  • toggle
  • 78.94 %
Validation stages
V1
83.33%
V2
90.91%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 45.000s 7441.115us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 87.537us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 51.907us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 363.716us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 32.260us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 158.380us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 51.907us 1 1 100.00
mbx_csr_aliasing 2.000s 32.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 54.000s 9669.896us 1 1 100.00
mbx_max_activity 1 1 100.00
mbx_stress_zero_delays 16.000s 2519.566us 1 1 100.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 24.000s 1488.649us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 13.000s 571.893us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 30.529us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 21.979us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 1.868us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 1.868us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 87.537us 1 1 100.00
mbx_csr_rw 2.000s 51.907us 1 1 100.00
mbx_csr_aliasing 2.000s 32.260us 1 1 100.00
mbx_same_csr_outstanding 2.000s 282.594us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 87.537us 1 1 100.00
mbx_csr_rw 2.000s 51.907us 1 1 100.00
mbx_csr_aliasing 2.000s 32.260us 1 1 100.00
mbx_same_csr_outstanding 2.000s 282.594us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 175.136us 1 1 100.00
mbx_sec_cm 1.000s 83.700us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:622) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 25689767406304501423661870981861617343456826551206946170909220850997478432441 85
TL item was: req: (cip_tl_seq_item@18485) { a_addr: 'h5ec08b30 a_data: 'h605458ec a_mask: 'ha a_size: 'h2 a_param: 'h0 a_source: 'hc2 a_opcode: 'h1 a_user: 'h27c94 d_param: 'h0 d_source: 'hc2 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 1867636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 40901875060131627549525814211584890545941364649858302268259304823610421140232 86
TL item was: req: (cip_tl_seq_item@20605) { a_addr: 'h62851c54 a_data: 'h59222e25 a_mask: 'h7 a_size: 'h2 a_param: 'h0 a_source: 'h76 a_opcode: 'h1 a_user: 'h2499d d_param: 'h0 d_source: 'h76 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 158379955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---