Simulation Results: otbn

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.44 %
  • code
  • 86.12 %
  • assert
  • 89.90 %
  • func
  • 98.31 %
  • block
  • 99.26 %
  • line
  • 99.46 %
  • branch
  • 94.69 %
  • toggle
  • 84.14 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
88.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 16.000s 71.528us 1 1 100.00
otbn_smoke_vectorized 7.000s 38.233us 1 1 100.00
single_binary 1 1 100.00
otbn_single 16.000s 45.137us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 20.137us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 46.163us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 60.793us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 47.307us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 8.000s 126.612us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 46.163us 1 1 100.00
otbn_csr_aliasing 4.000s 47.307us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 61.000s 1520.115us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 32.000s 1119.466us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 34.000s 354.736us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 79.000s 336.580us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 40.000s 117.378us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 90.000s 299.466us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 6.000s 96.412us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 27.361us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 9.000s 74.537us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 6.000s 21.064us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 45.343us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 83.885us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 83.885us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 5.000s 20.137us 1 1 100.00
otbn_csr_rw 4.000s 46.163us 1 1 100.00
otbn_csr_aliasing 4.000s 47.307us 1 1 100.00
otbn_same_csr_outstanding 4.000s 52.861us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 5.000s 20.137us 1 1 100.00
otbn_csr_rw 4.000s 46.163us 1 1 100.00
otbn_csr_aliasing 4.000s 47.307us 1 1 100.00
otbn_same_csr_outstanding 4.000s 52.861us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 8.000s 13.760us 1 1 100.00
otbn_dmem_err 12.000s 35.154us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 12.000s 57.555us 1 1 100.00
otbn_controller_ispr_rdata_err 17.000s 49.070us 1 1 100.00
otbn_mac_bignum_acc_err 7.000s 88.151us 1 1 100.00
otbn_urnd_err 7.000s 10.280us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 48.304us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 21.620us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 16.096us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 180.000s 865.763us 1 1 100.00
otbn_tl_intg_err 11.000s 63.881us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 4.000s 6.739us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 180.000s 865.763us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 180.000s 865.763us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 16.000s 71.528us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 12.000s 35.154us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 8.000s 13.760us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 11.000s 63.881us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 96.412us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 13.760us 1 1 100.00
otbn_dmem_err 12.000s 35.154us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 27.361us 1 1 100.00
otbn_illegal_mem_acc 5.000s 48.304us 1 1 100.00
otbn_sec_cm 180.000s 865.763us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 180.000s 865.763us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 16.000s 45.137us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 13.760us 1 1 100.00
otbn_dmem_err 12.000s 35.154us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 27.361us 1 1 100.00
otbn_illegal_mem_acc 5.000s 48.304us 1 1 100.00
otbn_sec_cm 180.000s 865.763us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 180.000s 865.763us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 96.412us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 13.760us 1 1 100.00
otbn_dmem_err 12.000s 35.154us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 27.361us 1 1 100.00
otbn_illegal_mem_acc 5.000s 48.304us 1 1 100.00
otbn_sec_cm 180.000s 865.763us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 180.000s 865.763us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 16.000s 45.137us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 8.000s 19.073us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 8.000s 21.571us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 27.000s 331.308us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 27.000s 331.308us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 9.000s 22.135us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 180.000s 865.763us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 180.000s 865.763us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 10.000s 63.087us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 180.000s 865.763us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 180.000s 865.763us 1 1 100.00
sec_cm_loop_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 5.000s 4.923us 0 1 0.00
sec_cm_call_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 5.000s 4.923us 0 1 0.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 6.000s 30.917us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 16.000s 45.137us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 16.000s 45.137us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 16.000s 45.137us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 40.000s 117.378us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 16.000s 45.137us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 16.000s 45.137us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 6.000s 35.466us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 16.000s 45.137us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 180.000s 865.763us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 274.000s 4437.772us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_urnd_err 22562600001384190707260662610510596888636392954492342420775655984754569743657 117
UVM_ERROR @ 10280391 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 10280391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_stack_addr_integ_chk 75513511342438471154757647652922742893314532617263175772502007435590017525517 107
UVM_ERROR @ 4922744 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 4922744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 11063939509921415502626267609266232823001155682288596289779858962038644812265 86
UVM_INFO @ 6738821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---