Simulation Results: otp_ctrl

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.29 %
  • code
  • 70.70 %
  • assert
  • 93.09 %
  • func
  • 50.07 %
  • line
  • 87.24 %
  • branch
  • 83.58 %
  • cond
  • 85.51 %
  • toggle
  • 62.27 %
  • FSM
  • 34.88 %
Validation stages
V1
88.89%
V2
70.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.760s 59.927us 1 1 100.00
smoke 0 1 0.00
otp_ctrl_smoke 3.700s 425.795us 0 1 0.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.200s 176.411us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.290s 680.136us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 6.190s 5065.715us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 8.680s 399.201us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.360s 92.521us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.290s 680.136us 1 1 100.00
otp_ctrl_csr_aliasing 8.680s 399.201us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.350s 43.837us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.410s 70.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 113.400s 11143.329us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 1.690s 85.747us 0 1 0.00
partition_check 2 2 100.00
otp_ctrl_background_chks 8.670s 1095.495us 1 1 100.00
otp_ctrl_check_fail 6.610s 4517.247us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.610s 814.208us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 14.230s 8927.372us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 27.440s 4048.105us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 3.530s 312.496us 1 1 100.00
otp_ctrl_parallel_lc_esc 32.790s 5310.924us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 25.750s 1656.294us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 29.190s 3743.809us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 18.710s 2773.244us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 8.350s 1169.340us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.740s 91.512us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.990s 231.785us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.310s 176.186us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.310s 176.186us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.200s 176.411us 1 1 100.00
otp_ctrl_csr_rw 2.290s 680.136us 1 1 100.00
otp_ctrl_csr_aliasing 8.680s 399.201us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.370s 844.720us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.200s 176.411us 1 1 100.00
otp_ctrl_csr_rw 2.290s 680.136us 1 1 100.00
otp_ctrl_csr_aliasing 8.680s 399.201us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.370s 844.720us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
otp_ctrl_tl_intg_err 12.440s 1148.413us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 12.440s 1148.413us 1 1 100.00
sec_cm_secret_mem_scramble 0 1 0.00
otp_ctrl_smoke 3.700s 425.795us 0 1 0.00
sec_cm_part_mem_digest 0 1 0.00
otp_ctrl_smoke 3.700s 425.795us 0 1 0.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 32.790s 5310.924us 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.790s 5310.924us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.790s 5310.924us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 32.790s 5310.924us 1 1 100.00
otp_ctrl_macro_errs 29.190s 3743.809us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.790s 5310.924us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 32.790s 5310.924us 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 32.790s 5310.924us 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.790s 5310.924us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.790s 5310.924us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 32.790s 5310.924us 1 1 100.00
otp_ctrl_macro_errs 29.190s 3743.809us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.790s 5310.924us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 32.790s 5310.924us 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 1.690s 85.747us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 6.610s 4517.247us 1 1 100.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 14.230s 8927.372us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 14.230s 8927.372us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 14.230s 8927.372us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 14.230s 8927.372us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 14.230s 8927.372us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
otp_ctrl_smoke 3.700s 425.795us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 14.230s 8927.372us 0 1 0.00
sec_cm_test_bus_lc_gated 0 1 0.00
otp_ctrl_smoke 3.700s 425.795us 0 1 0.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 258.220s 16525.671us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.610s 814.208us 1 1 100.00
sec_cm_check_trigger_config_regwen 0 1 0.00
otp_ctrl_smoke 3.700s 425.795us 0 1 0.00
sec_cm_check_config_regwen 0 1 0.00
otp_ctrl_smoke 3.700s 425.795us 0 1 0.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 29.190s 3743.809us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 121.650s 68816.753us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.700s 64.294us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 3 test runs
otp_ctrl_smoke 106704819321866596925070918670173117054145163826178183851637386095826617425126 3146
UVM_INFO @ 425795037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_partition_walk 99857527087948052083488727651516516700986182983179793648347215489569999532046 160055
UVM_INFO @ 11143329064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 31850181036008864347707164983296962871877260288712324255879029901155938575538 493
UVM_INFO @ 85747157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 2 test runs
otp_ctrl_dai_lock 35594309745844817223814307390269880953997933879791220189486350064740824648813 6537
UVM_INFO @ 8927372355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 70985800009419279693634644464324896310112640731790633101386780534675724969037 13593
UVM_INFO @ 2773243714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 59870007902629238616732819768177719076430032551984931433721135230593537757418 89
UVM_INFO @ 68816753362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 1 test run
otp_ctrl_parallel_key_req 927416940733071187823440568467490394551453585649445014823417514893571734496 28132
UVM_INFO @ 4048104921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:2219) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 70591502795564939393614745076651475417221361110160091469678117811436078224714 92
UVM_INFO @ 64293715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:677) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_stress_all 103106784337715854255058217218394706569115924558619352299076075212152256816266 4995
UVM_INFO @ 1169340335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---