Simulation Results: rom_ctrl/64kb

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.95 %
  • code
  • 83.17 %
  • assert
  • 97.67 %
  • func
  • 95.01 %
  • block
  • 86.94 %
  • line
  • 86.21 %
  • branch
  • 86.11 %
  • toggle
  • 84.18 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.000s 2623.405us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 65.552us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.000s 165.304us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 120.238us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 88.945us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 57.778us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.000s 165.304us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 88.945us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 56.828us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 53.404us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 329.038us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 6.000s 419.233us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.000s 442.855us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 57.033us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 720.687us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 720.687us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 65.552us 1 1 100.00
rom_ctrl_csr_rw 2.000s 165.304us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 88.945us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 54.551us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 65.552us 1 1 100.00
rom_ctrl_csr_rw 2.000s 165.304us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 88.945us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 54.551us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1436.000s 1000000.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 5.000s 188.909us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 193.000s 1439.874us 1 1 100.00
rom_ctrl_tl_intg_err 21.000s 200.342us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 193.000s 1439.874us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 193.000s 1439.874us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1436.000s 1000000.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1436.000s 1000000.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1436.000s 1000000.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1436.000s 1000000.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1436.000s 1000000.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 193.000s 1439.874us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 193.000s 1439.874us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.000s 2623.405us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.000s 2623.405us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.000s 2623.405us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 21.000s 200.342us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 1436.000s 1000000.000us 0 1 0.00
rom_ctrl_kmac_err_chk 7.000s 442.855us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1436.000s 1000000.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1436.000s 1000000.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 1436.000s 1000000.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 5.000s 188.909us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 193.000s 1439.874us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 13.000s 2485.081us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 71089459792277874138284825507864287151605784475405837385003730263009578370872 88
UVM_INFO @ 329038100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rom_ctrl_corrupt_sig_fatal_chk 91322793945284961030950220724409139284966881943454132096583493246484181953884 87
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---