Simulation Results: rstmgr

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.26 %
  • code
  • 99.32 %
  • assert
  • 98.17 %
  • func
  • 94.28 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.86 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.190s 70.980us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.940s 63.639us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.250s 37.166us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.170s 207.692us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.200s 40.247us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.450s 96.354us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.250s 37.166us 1 1 100.00
rstmgr_csr_aliasing 1.200s 40.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.630s 123.095us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.000s 45.141us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.120s 100.172us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.840s 576.867us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.840s 576.867us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.840s 576.867us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.840s 576.867us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 4.440s 650.912us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.960s 36.720us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.360s 41.097us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.360s 41.097us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.940s 63.639us 1 1 100.00
rstmgr_csr_rw 1.250s 37.166us 1 1 100.00
rstmgr_csr_aliasing 1.200s 40.247us 1 1 100.00
rstmgr_same_csr_outstanding 1.320s 74.683us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.940s 63.639us 1 1 100.00
rstmgr_csr_rw 1.250s 37.166us 1 1 100.00
rstmgr_csr_aliasing 1.200s 40.247us 1 1 100.00
rstmgr_same_csr_outstanding 1.320s 74.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 17.690s 3444.568us 1 1 100.00
rstmgr_tl_intg_err 2.650s 325.802us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 17.690s 3444.568us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 17.690s 3444.568us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.650s 325.802us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.110s 62.679us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.030s 482.913us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.700s 292.956us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 17.690s 3444.568us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.250s 37.166us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.250s 37.166us 1 1 100.00