Simulation Results: rv_dm/use_dmi_interface

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.15 %
  • code
  • 80.90 %
  • assert
  • 96.66 %
  • func
  • 92.90 %
  • block
  • 92.18 %
  • line
  • 92.90 %
  • branch
  • 78.75 %
  • toggle
  • 73.37 %
  • FSM
  • 78.57 %
Validation stages
V1
92.59%
V2
73.91%
V2S
85.71%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 32.000s 904.431us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 34.000s 567.459us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 32.000s 637.898us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 32.000s 13940.666us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 30.000s 1077.164us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 32.000s 8484.283us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 31.000s 1856.756us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 50.000s 16858.423us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 86.000s 39926.721us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 35.000s 976.845us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 35.000s 971.548us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 35.000s 720.862us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 30.000s 195.888us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 33.000s 225.379us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 34.000s 375.152us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 31.000s 199.802us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 31.000s 355.522us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 35.000s 976.845us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 32.000s 625.930us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 32.000s 151.915us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 35.000s 720.862us 1 1 100.00
rom_read_access 0 1 0.00
rv_dm_rom_read_access 31.000s 27.278us 0 1 0.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 33.000s 108.183us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 34.000s 934.583us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 46.000s 4204.720us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 61.000s 4668.218us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 32.000s 142.809us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 61.000s 4668.218us 1 1 100.00
rv_dm_csr_rw 34.000s 934.583us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 30.000s 85.833us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 30.000s 147.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 32.000s 904.431us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 33.000s 429.501us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 30.000s 278.413us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 32.000s 153.721us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 33.000s 2056.466us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 37.000s 3113.706us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 32.000s 64.061us 0 1 0.00
bad_sba 1 1 100.00
rv_dm_bad_sba_tl_access 33.000s 2074.759us 1 1 100.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 37.000s 4378.252us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 35.000s 524.866us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 34.000s 2005.185us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 30.000s 536.310us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 31.000s 102.897us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm 34.000s 7531.931us 1 1 100.00
rv_dm_tap_fsm_rand_reset 54.000s 9920.384us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 33.000s 302.259us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 30.000s 773.704us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 33.000s 81.056us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 36.000s 222.522us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 36.000s 222.522us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 61.000s 4668.218us 1 1 100.00
rv_dm_csr_hw_reset 33.000s 108.183us 1 1 100.00
rv_dm_csr_rw 34.000s 934.583us 1 1 100.00
rv_dm_same_csr_outstanding 34.000s 207.611us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 61.000s 4668.218us 1 1 100.00
rv_dm_csr_hw_reset 33.000s 108.183us 1 1 100.00
rv_dm_csr_rw 34.000s 934.583us 1 1 100.00
rv_dm_same_csr_outstanding 34.000s 207.611us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 30.000s 727.397us 1 1 100.00
rv_dm_tl_intg_err 38.000s 2856.761us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 38.000s 2856.761us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 34.000s 2005.185us 1 1 100.00
rv_dm_debug_disabled 33.000s 91.090us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 34.000s 2005.185us 1 1 100.00
rv_dm_debug_disabled 33.000s 91.090us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 32.000s 904.431us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 0 1 0.00
rv_dm_buffered_enable 33.000s 142.901us 0 1 0.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 32.000s 320.501us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 32.000s 320.501us 1 1 100.00
sec_cm_exec_ctrl_mubi 0 1 0.00
rv_dm_buffered_enable 33.000s 142.901us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 38.000s 2853.143us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 277.000s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:480) [scoreboard] sba_tl_access_q item uncompared: 2 test runs
rv_dm_sba_tl_access 91871716084707719497230788905021371555362897533625753039148704875361797376857 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23813
rv_dm_autoincr_sba_tl_access 19757000667480738895903538159716686061855162101995358174399447800809413720300 168
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @24025
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*]) 2 test runs
rv_dm_hart_unavail 63619265369357524960975437841569426827840941351044105798003072555261339732135 87
UVM_INFO @ 102897062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 59490089682707320766844564498911936623226641521131444604229687171895439025025 91
UVM_INFO @ 773704280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp 1 test run
rv_dm_delayed_resp_sba_tl_access 102538189372371634250501190357760538533012586371380223844557343820179493422867 107
UVM_INFO @ 64060986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*]) 1 test run
rv_dm_mem_tl_access_resuming 70877967941138504791512194881516000991270778554633597841694523590852184182067 87
UVM_INFO @ 195888496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) 1 test run
rv_dm_jtag_dmi_debug_disabled 88937967686333253769576189523348008745298764678310016362782387785891841291557 87
UVM_INFO @ 524866104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=*, but it was *"}. Item: (req: (cip_tl_seq_item@23859) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } 1 test run
rv_dm_rom_read_access 81236214304680072143408200166944482068705077707160988878043742122463916556232 87
).
UVM_INFO @ 27277616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [*] vs * [*]) 1 test run
rv_dm_buffered_enable 28369402821964502310145142820996863624281132721637830019706430387810115154813 89
UVM_INFO @ 142900768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rv_dm_scanmode 90601658680703885080557178439505938503228180087521000210298725911708877776869 87
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done) 1 test run
rv_dm_stress_all_with_rand_reset 3523949636138057041817568495385791134665594106565129328961610052152490025389 107
UVM_INFO @ 2853143475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---