Simulation Results: rv_timer

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.66 %
  • code
  • 90.45 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.000s 463.263us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 64.321us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 33.590us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 164.028us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 25.741us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 43.283us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 33.590us 1 1 100.00
rv_timer_csr_aliasing 1.000s 25.741us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 1.000s 48.449us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 651.827us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 6.000s 25597.505us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 6.000s 25597.505us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 4.000s 7874.133us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 40.565us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 26.920us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 311.935us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 311.935us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 64.321us 1 1 100.00
rv_timer_csr_rw 1.000s 33.590us 1 1 100.00
rv_timer_csr_aliasing 1.000s 25.741us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 26.020us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 64.321us 1 1 100.00
rv_timer_csr_rw 1.000s 33.590us 1 1 100.00
rv_timer_csr_aliasing 1.000s 25.741us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 26.020us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 157.698us 1 1 100.00
rv_timer_tl_intg_err 1.000s 242.179us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 242.179us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 2.000s 113.427us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 2.000s 133.574us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 24.000s 17489.891us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 100706794989278351877587471049905539370719223651854450263811186455454339760421 84
UVM_INFO @ 113427450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:347) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 21708144956721681079342086436411046918094426233603978954049158749950636061147 84
UVM_INFO @ 133574309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---