Simulation Results: spi_device/1r1w

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.19 %
  • code
  • 89.51 %
  • assert
  • 95.40 %
  • func
  • 64.67 %
  • block
  • 98.33 %
  • line
  • 98.75 %
  • branch
  • 96.96 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 314.000s 100903.406us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 106.005us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.000s 21.428us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 14.000s 1179.123us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 14.000s 3536.221us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.000s 59.476us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.000s 21.428us 1 1 100.00
spi_device_csr_aliasing 14.000s 3536.221us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 12.243us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 50.236us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.000s 32.214us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 1.406us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 3.334us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.000s 11.032us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.000s 11.032us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.000s 11.406us 1 1 100.00
spi_device_tpm_sts_read 2.000s 50.848us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 27.000s 4824.075us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 8.000s 1144.016us 1 1 100.00
spi_device_flash_all 70.000s 6505.332us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.000s 223.336us 1 1 100.00
spi_device_flash_all 70.000s 6505.332us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.000s 223.336us 1 1 100.00
spi_device_flash_all 70.000s 6505.332us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 70.000s 6505.332us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 9.000s 585.523us 1 1 100.00
spi_device_flash_all 70.000s 6505.332us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 9.000s 585.523us 1 1 100.00
spi_device_flash_all 70.000s 6505.332us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 9.000s 585.523us 1 1 100.00
spi_device_flash_all 70.000s 6505.332us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 9.000s 585.523us 1 1 100.00
spi_device_flash_all 70.000s 6505.332us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 9.000s 585.523us 1 1 100.00
spi_device_flash_all 70.000s 6505.332us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.000s 50.739us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 9.000s 655.229us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 9.000s 655.229us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 9.000s 655.229us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 10.000s 244.763us 1 1 100.00
spi_device_read_buffer_direct 14.000s 864.982us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 9.000s 655.229us 1 1 100.00
spi_device_flash_all 70.000s 6505.332us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 70.000s 6505.332us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 70.000s 6505.332us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.000s 83.851us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.000s 83.851us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 78.000s 26477.561us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 314.000s 100903.406us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 46.000s 3228.915us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 2.000s 178.639us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 13.816us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 12.954us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.000s 177.512us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.000s 177.512us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 106.005us 1 1 100.00
spi_device_csr_rw 2.000s 21.428us 1 1 100.00
spi_device_csr_aliasing 14.000s 3536.221us 1 1 100.00
spi_device_same_csr_outstanding 2.000s 176.220us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 106.005us 1 1 100.00
spi_device_csr_rw 2.000s 21.428us 1 1 100.00
spi_device_csr_aliasing 14.000s 3536.221us 1 1 100.00
spi_device_same_csr_outstanding 2.000s 176.220us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 114.807us 1 1 100.00
spi_device_tl_intg_err 19.000s 3305.909us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 19.000s 3305.909us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 52690811825158870838174028862840637231683248057316520739524894421124030281579 87
UVM_ERROR @ 1221878 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[974] not found within the scope .
UVM_ERROR @ 1221878 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[974] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 22170138216607085434684622994283609557218791103534068608629599015899682335276 85
UVM_ERROR @ 922964 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x236 [1000110110] vs 0x0 [0])
UVM_ERROR @ 985964 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x44 [1000100] vs 0x0 [0])
UVM_ERROR @ 1005964 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x31 [110001] vs 0x0 [0])
UVM_ERROR @ 1009964 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x313 [1100010011] vs 0x0 [0])