Simulation Results: spi_host

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.87 %
  • code
  • 91.30 %
  • assert
  • 95.65 %
  • func
  • 88.66 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 12.000s 869.747us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 40.959us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 190.724us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 4.000s 256.612us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 31.085us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 136.930us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 190.724us 1 1 100.00
spi_host_csr_aliasing 2.000s 31.085us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 19.992us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 32.100us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 37.708us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 123.818us 1 1 100.00
spi_host_error_cmd 1.000s 22.668us 1 1 100.00
spi_host_event 6.000s 240.299us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 62.734us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 62.734us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 62.734us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 18.000s 677.048us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 3.000s 152.184us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 280.271us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 62.734us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 62.734us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 12.000s 869.747us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 12.000s 869.747us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 7.000s 1067.293us 1 1 100.00
spien 1 1 100.00
spi_host_spien 52.000s 17413.805us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 253.000s 128810.992us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 1.000s 43.534us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 123.818us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 26.410us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 19.667us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 151.729us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 151.729us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 40.959us 1 1 100.00
spi_host_csr_rw 1.000s 190.724us 1 1 100.00
spi_host_csr_aliasing 2.000s 31.085us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 116.234us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 40.959us 1 1 100.00
spi_host_csr_rw 1.000s 190.724us 1 1 100.00
spi_host_csr_aliasing 2.000s 31.085us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 116.234us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 159.537us 1 1 100.00
spi_host_sec_cm 2.000s 46.969us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 159.537us 1 1 100.00