Simulation Results: sram_ctrl/ret

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.63 %
  • code
  • 82.40 %
  • assert
  • 98.08 %
  • func
  • 94.40 %
  • block
  • 93.88 %
  • line
  • 94.98 %
  • branch
  • 89.64 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 119.463us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 28.739us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 43.392us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 220.202us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.112us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 374.529us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 43.392us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.112us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 10.000s 3236.895us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 407.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 3.000s 246.873us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 149.000s 11806.100us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 965.298us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 16.000s 1311.207us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 2.000s 350.330us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 7.000s 1125.628us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 48.232us 1 1 100.00
sram_ctrl_partial_access_b2b 210.000s 33472.580us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 329.038us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.000s 71.831us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 44.628us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 311.640us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 94.928us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 18.000s 747.100us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 34.859us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 144.672us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 144.672us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 28.739us 1 1 100.00
sram_ctrl_csr_rw 2.000s 43.392us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.112us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 62.253us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 28.739us 1 1 100.00
sram_ctrl_csr_rw 2.000s 43.392us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.112us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 62.253us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 1367.465us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 362.512us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 326.528us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 362.512us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 326.528us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 311.640us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 311.640us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 43.392us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 7.000s 1125.628us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 1125.628us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 1125.628us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 2.000s 350.330us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 52.995us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 1367.465us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 257.952us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 119.463us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 119.463us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 7.000s 1125.628us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 362.512us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 2.000s 350.330us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 362.512us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 362.512us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 119.463us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 362.512us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 37.000s 11383.736us 1 1 100.00