Simulation Results: uart

 
11/08/2026 19:53:31 DVSim: v1.50.1 sha: 49df6ac json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.00 %
  • code
  • 92.73 %
  • assert
  • 98.56 %
  • func
  • 90.69 %
  • block
  • 99.08 %
  • line
  • 99.52 %
  • branch
  • 98.34 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.000s 679.436us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 3.000s 1031.640us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 12.180us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 45.745us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 73.566us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 15.106us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 12.180us 1 1 100.00
uart_csr_aliasing 1.000s 73.566us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 58.000s 46704.608us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.000s 679.436us 1 1 100.00
uart_tx_rx 58.000s 46704.608us 1 1 100.00
parity_error 2 2 100.00
uart_intr 31.000s 47472.451us 1 1 100.00
uart_rx_parity_err 114.000s 119972.943us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 58.000s 46704.608us 1 1 100.00
uart_intr 31.000s 47472.451us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 18.000s 39350.075us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 27.000s 18676.981us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 46.000s 183458.804us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 31.000s 47472.451us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 31.000s 47472.451us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 31.000s 47472.451us 1 1 100.00
perf 1 1 100.00
uart_perf 305.000s 14941.381us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.000s 4281.449us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.000s 4281.449us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 7.000s 9779.818us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 44.000s 36605.381us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 20.000s 6684.911us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 8.000s 2453.189us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 259.000s 195983.619us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 17.000s 48895.187us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 20.558us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 25.357us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 3.000s 498.699us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 3.000s 498.699us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 3.000s 1031.640us 1 1 100.00
uart_csr_rw 1.000s 12.180us 1 1 100.00
uart_csr_aliasing 1.000s 73.566us 1 1 100.00
uart_same_csr_outstanding 2.000s 88.801us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 3.000s 1031.640us 1 1 100.00
uart_csr_rw 1.000s 12.180us 1 1 100.00
uart_csr_aliasing 1.000s 73.566us 1 1 100.00
uart_same_csr_outstanding 2.000s 88.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 67.182us 1 1 100.00
uart_tl_intg_err 1.000s 199.617us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 199.617us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 10.000s 1115.843us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 85203457695311716471713205397220649879775809564305146342311716368033728154258 85
UVM_ERROR @ 8696499736 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 8696520144 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (237 [0xed] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 8696560960 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 8696581368 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (237 [0xed] vs 255 [0xff]) reg name: uart_reg_block.rdata