Simulation Results: ac_range_check

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.91 %
  • code
  • 93.09 %
  • assert
  • 97.75 %
  • func
  • 57.88 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.09 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 28.000s 1552.010us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 35.000s 3607.390us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 552.442us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 49.496us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 31.000s 26444.462us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 18.000s 4550.975us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 1.000s 180.258us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 49.496us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 4550.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 73.109us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 28.000s 8460.433us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 194.000s 20463.911us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 1.000s 83.872us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 14.259us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 95.198us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 95.198us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 552.442us 1 1 100.00
ac_range_check_csr_rw 2.000s 49.496us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 4550.975us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 171.690us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 552.442us 1 1 100.00
ac_range_check_csr_rw 2.000s 49.496us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 4550.975us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 171.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 3609.784us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 3609.784us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 3609.784us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 3609.784us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 79.000s 9235.371us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 14.013us 1 1 100.00
ac_range_check_tl_intg_err 7.000s 394.553us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 255.000s 496.126us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 18.000s 418.571us 1 1 100.00