Simulation Results: aes/gcm_masked

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.04 %
  • code
  • 95.16 %
  • assert
  • 98.29 %
  • func
  • 64.68 %
  • block
  • 95.79 %
  • line
  • 97.51 %
  • branch
  • 89.58 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
94.74%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 148.088us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 188.466us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 64.665us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 76.284us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 250.992us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 335.571us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 58.800us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 76.284us 1 1 100.00
aes_csr_aliasing 3.000s 335.571us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 188.466us 1 1 100.00
aes_config_error 2.000s 214.104us 1 1 100.00
aes_stress 3.000s 88.214us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 188.466us 1 1 100.00
aes_config_error 2.000s 214.104us 1 1 100.00
aes_stress 3.000s 88.214us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 88.214us 1 1 100.00
aes_b2b 5.000s 125.561us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 88.214us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 188.466us 1 1 100.00
aes_config_error 2.000s 214.104us 1 1 100.00
aes_stress 3.000s 88.214us 1 1 100.00
aes_alert_reset 5.000s 212.353us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 66.249us 1 1 100.00
aes_config_error 2.000s 214.104us 1 1 100.00
aes_alert_reset 5.000s 212.353us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 102.207us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 236.539us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 7.000s 231.422us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 5.000s 212.353us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 88.214us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 88.214us 1 1 100.00
aes_sideload 3.000s 191.917us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 109.988us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10802.096s 0.000us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 106.943us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 56.657us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 908.240us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 908.240us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 64.665us 1 1 100.00
aes_csr_rw 2.000s 76.284us 1 1 100.00
aes_csr_aliasing 3.000s 335.571us 1 1 100.00
aes_same_csr_outstanding 2.000s 75.482us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 64.665us 1 1 100.00
aes_csr_rw 2.000s 76.284us 1 1 100.00
aes_csr_aliasing 3.000s 335.571us 1 1 100.00
aes_same_csr_outstanding 2.000s 75.482us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 4.000s 158.677us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 5.000s 127.779us 0 1 0.00
aes_control_fi 1.000s 55.673us 1 1 100.00
aes_cipher_fi 3.000s 60.189us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 118.259us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 118.259us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 118.259us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 118.259us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 339.311us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 1085.459us 1 1 100.00
aes_tl_intg_err 2.000s 97.437us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 97.437us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 5.000s 212.353us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 118.259us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 118.259us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 188.466us 1 1 100.00
aes_stress 3.000s 88.214us 1 1 100.00
aes_alert_reset 5.000s 212.353us 1 1 100.00
aes_core_fi 26.000s 10007.365us 0 1 0.00
sec_cm_gcm_config_sparse 3 4 75.00
aes_gcm_save_restore 2.000s 106.943us 1 1 100.00
aes_config_error 2.000s 214.104us 1 1 100.00
aes_stress 3.000s 88.214us 1 1 100.00
aes_core_fi 26.000s 10007.365us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 118.259us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 113.272us 1 1 100.00
aes_stress 3.000s 88.214us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 88.214us 1 1 100.00
aes_sideload 3.000s 191.917us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 113.272us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 113.272us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 113.272us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 113.272us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 113.272us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 88.214us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 88.214us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 5.000s 127.779us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 5.000s 127.779us 0 1 0.00
aes_control_fi 1.000s 55.673us 1 1 100.00
aes_cipher_fi 3.000s 60.189us 1 1 100.00
aes_ctr_fi 2.000s 91.948us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 5.000s 127.779us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 5.000s 127.779us 0 1 0.00
aes_control_fi 1.000s 55.673us 1 1 100.00
aes_cipher_fi 3.000s 60.189us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 60.189us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 5.000s 127.779us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 5.000s 127.779us 0 1 0.00
aes_control_fi 1.000s 55.673us 1 1 100.00
aes_ctr_fi 2.000s 91.948us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 5.000s 127.779us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 5.000s 127.779us 0 1 0.00
aes_control_fi 1.000s 55.673us 1 1 100.00
aes_cipher_fi 3.000s 60.189us 1 1 100.00
aes_ctr_fi 2.000s 91.948us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 5.000s 212.353us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 5.000s 127.779us 0 1 0.00
aes_control_fi 1.000s 55.673us 1 1 100.00
aes_cipher_fi 3.000s 60.189us 1 1 100.00
aes_ctr_fi 2.000s 91.948us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 5.000s 127.779us 0 1 0.00
aes_control_fi 1.000s 55.673us 1 1 100.00
aes_cipher_fi 3.000s 60.189us 1 1 100.00
aes_ctr_fi 2.000s 91.948us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 5.000s 127.779us 0 1 0.00
aes_control_fi 1.000s 55.673us 1 1 100.00
aes_ctr_fi 2.000s 91.948us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 1.000s 71.393us 1 1 100.00
aes_fi 5.000s 127.779us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 5.000s 127.779us 0 1 0.00
aes_control_fi 1.000s 55.673us 1 1 100.00
aes_cipher_fi 3.000s 60.189us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 9.000s 684.760us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 27682591155454520616539204636299639493830305853139462948692581339736722284511 12153
UVM_INFO @ 158676741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 47169141872057459763293983704583854732195342802761955452672553365553056193573 22366
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 1 test run
aes_core_fi 28395888930528309238885759107707278782787302934038890064472855764903384106694 147
UVM_INFO @ 10007364539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
aes_stress_all 10764096098318544105607036217170126719379067162413412827160569433798394779332 None
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 15200945786439724981024353112462666956477589344571165125319847043079332608431 368
UVM_INFO @ 684760216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---