Simulation Results: aes/gcm_unmasked

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.19 %
  • code
  • 90.25 %
  • assert
  • 97.75 %
  • func
  • 61.57 %
  • block
  • 90.18 %
  • line
  • 92.35 %
  • branch
  • 81.91 %
  • toggle
  • 98.08 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 64.594us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 72.939us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 116.044us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 91.495us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 1471.362us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 222.561us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 59.907us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 91.495us 1 1 100.00
aes_csr_aliasing 2.000s 222.561us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 72.939us 1 1 100.00
aes_config_error 2.000s 70.582us 1 1 100.00
aes_stress 2.000s 82.344us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 72.939us 1 1 100.00
aes_config_error 2.000s 70.582us 1 1 100.00
aes_stress 2.000s 82.344us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 82.344us 1 1 100.00
aes_b2b 2.000s 194.720us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 82.344us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 72.939us 1 1 100.00
aes_config_error 2.000s 70.582us 1 1 100.00
aes_stress 2.000s 82.344us 1 1 100.00
aes_alert_reset 3.000s 436.011us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 75.565us 1 1 100.00
aes_config_error 2.000s 70.582us 1 1 100.00
aes_alert_reset 3.000s 436.011us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 244.887us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 856.143us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 436.011us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 82.344us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 82.344us 1 1 100.00
aes_sideload 2.000s 172.394us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 60.585us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 6.000s 458.305us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 164.735us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 1836.030us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 1836.030us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 116.044us 1 1 100.00
aes_csr_rw 1.000s 91.495us 1 1 100.00
aes_csr_aliasing 2.000s 222.561us 1 1 100.00
aes_same_csr_outstanding 2.000s 256.445us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 116.044us 1 1 100.00
aes_csr_rw 1.000s 91.495us 1 1 100.00
aes_csr_aliasing 2.000s 222.561us 1 1 100.00
aes_same_csr_outstanding 2.000s 256.445us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 556.948us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 265.999us 0 1 0.00
aes_control_fi 3.000s 62.368us 1 1 100.00
aes_cipher_fi 2.000s 79.346us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 110.445us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 110.445us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 110.445us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 110.445us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 225.467us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 1134.465us 1 1 100.00
aes_tl_intg_err 3.000s 597.583us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 597.583us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 436.011us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 110.445us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 110.445us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 72.939us 1 1 100.00
aes_stress 2.000s 82.344us 1 1 100.00
aes_alert_reset 3.000s 436.011us 1 1 100.00
aes_core_fi 2.000s 91.349us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 70.582us 1 1 100.00
aes_stress 2.000s 82.344us 1 1 100.00
aes_core_fi 2.000s 91.349us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 110.445us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 63.140us 1 1 100.00
aes_stress 2.000s 82.344us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 82.344us 1 1 100.00
aes_sideload 2.000s 172.394us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 63.140us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 63.140us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 63.140us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 63.140us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 63.140us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 82.344us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 82.344us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 265.999us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 265.999us 0 1 0.00
aes_control_fi 3.000s 62.368us 1 1 100.00
aes_cipher_fi 2.000s 79.346us 1 1 100.00
aes_ctr_fi 2.000s 58.179us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 265.999us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 265.999us 0 1 0.00
aes_control_fi 3.000s 62.368us 1 1 100.00
aes_cipher_fi 2.000s 79.346us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 79.346us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 265.999us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 265.999us 0 1 0.00
aes_control_fi 3.000s 62.368us 1 1 100.00
aes_ctr_fi 2.000s 58.179us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 265.999us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 265.999us 0 1 0.00
aes_control_fi 3.000s 62.368us 1 1 100.00
aes_cipher_fi 2.000s 79.346us 1 1 100.00
aes_ctr_fi 2.000s 58.179us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 436.011us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 265.999us 0 1 0.00
aes_control_fi 3.000s 62.368us 1 1 100.00
aes_cipher_fi 2.000s 79.346us 1 1 100.00
aes_ctr_fi 2.000s 58.179us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 265.999us 0 1 0.00
aes_control_fi 3.000s 62.368us 1 1 100.00
aes_cipher_fi 2.000s 79.346us 1 1 100.00
aes_ctr_fi 2.000s 58.179us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 265.999us 0 1 0.00
aes_control_fi 3.000s 62.368us 1 1 100.00
aes_ctr_fi 2.000s 58.179us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 265.999us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 265.999us 0 1 0.00
aes_control_fi 3.000s 62.368us 1 1 100.00
aes_cipher_fi 2.000s 79.346us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 65.334us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 100046477332119697002775173444648416117738895005788117745677551458545789489195 3975
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
UVM_FATAL (aes_scoreboard.sv:785) scoreboard [scoreboard] # * 1 test run
aes_stress_all 80333968641296857448519604510916178768803827340054161126995396771832961665106 24464
TEST FAILED MESSAGES DID NOT MATCH
0 1f 68 68 0
1 00 c8 c8 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 78139617835291071853668143712812683985448329847005164880359245272394376307080 187
UVM_INFO @ 65333967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---