Simulation Results: alert_handler

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.62 %
  • code
  • 90.02 %
  • assert
  • 97.93 %
  • func
  • 74.91 %
  • line
  • 99.71 %
  • branch
  • 98.35 %
  • cond
  • 92.06 %
  • toggle
  • 84.18 %
  • FSM
  • 75.81 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 24.380s 597.734us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 7.940s 153.860us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.290s 141.061us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 197.090s 11519.731us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 220.540s 9078.856us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 10.800s 842.531us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.290s 141.061us 1 1 100.00
alert_handler_csr_aliasing 220.540s 9078.856us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 189.790s 5257.832us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 10.930s 120.993us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1509.340s 135168.551us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 41.110s 960.658us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 24.380s 597.734us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 23.580s 407.673us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 6.530s 172.288us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 122.460s 4668.500us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1577.960s 295290.088us 1 1 100.00
alert_handler_lpg_stub_clk 689.040s 9328.664us 1 1 100.00
stress_all 0 1 0.00
alert_handler_stress_all 1344.940s 32122.172us 0 1 0.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 9.180s 233.438us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.520s 133.845us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.410s 7.730us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 22.560s 427.452us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 22.560s 427.452us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 7.940s 153.860us 1 1 100.00
alert_handler_csr_rw 4.290s 141.061us 1 1 100.00
alert_handler_csr_aliasing 220.540s 9078.856us 1 1 100.00
alert_handler_same_csr_outstanding 19.380s 380.366us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 7.940s 153.860us 1 1 100.00
alert_handler_csr_rw 4.290s 141.061us 1 1 100.00
alert_handler_csr_aliasing 220.540s 9078.856us 1 1 100.00
alert_handler_same_csr_outstanding 19.380s 380.366us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 289.680s 5558.078us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 289.680s 5558.078us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 289.680s 5558.078us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 289.680s 5558.078us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 475.760s 7489.512us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 20.760s 562.355us 1 1 100.00
alert_handler_tl_intg_err 34.730s 5229.898us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 34.730s 5229.898us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 289.680s 5558.078us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 24.380s 597.734us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 24.380s 597.734us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 24.380s 597.734us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 24.380s 597.734us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 41.110s 960.658us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1577.960s 295290.088us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 41.110s 960.658us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1509.340s 135168.551us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1509.340s 135168.551us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 20.760s 562.355us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 20.760s 562.355us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 20.760s 562.355us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 20.760s 562.355us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 20.760s 562.355us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 20.760s 562.355us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 20.760s 562.355us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 20.760s 562.355us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 20.760s 562.355us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 299.710s 21695.497us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 86733767549886301491214120135431285974518397750302195148416289488944204759279 226
UVM_INFO @ 233437589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_accum_cnt 1 test run
alert_handler_stress_all 94227798712478961396861108077127552711991904139551534640598578435646262345889 86
UVM_INFO @ 32122171531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 31501097822718696149575276975550152548086492516198872349794007934325165075407 341
UVM_INFO @ 21695496899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---