Simulation Results: clkmgr

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.12 %
  • code
  • 68.51 %
  • assert
  • 88.84 %
  • func
  • 68.02 %
  • line
  • 81.56 %
  • branch
  • 86.53 %
  • cond
  • 77.21 %
  • toggle
  • 97.26 %
  • FSM
  • 0.00 %
Validation stages
V1
66.67%
V2
61.54%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.160s 62.034us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.830s 18.500us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.610s 1.911us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.550s 1.452us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.320s 25.593us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.640s 118.307us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.610s 1.911us 0 1 0.00
clkmgr_csr_aliasing 1.320s 25.593us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.880s 34.004us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.940s 24.235us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.920s 43.387us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.160s 62.034us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.660s 7.497us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.730s 3.117us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.660s 7.497us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.700s 97.628us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.830s 19.294us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.670s 97.366us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.670s 97.366us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.830s 18.500us 1 1 100.00
clkmgr_csr_rw 0.610s 1.911us 0 1 0.00
clkmgr_csr_aliasing 1.320s 25.593us 1 1 100.00
clkmgr_same_csr_outstanding 0.570s 2.294us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.830s 18.500us 1 1 100.00
clkmgr_csr_rw 0.610s 1.911us 0 1 0.00
clkmgr_csr_aliasing 1.320s 25.593us 1 1 100.00
clkmgr_same_csr_outstanding 0.570s 2.294us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 3.010s 252.558us 0 1 0.00
clkmgr_tl_intg_err 0.670s 5.894us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.100s 48.152us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.100s 48.152us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.100s 48.152us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.100s 48.152us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.970s 32.224us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.670s 5.894us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.660s 7.497us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.730s 3.117us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.100s 48.152us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.550s 89.771us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.610s 1.911us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 3.010s 252.558us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.610s 1.911us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.610s 1.911us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 3.010s 252.558us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.730s 14.718us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.930s 24.112us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 103348768967931622449537220927322819920148819998119029026532106685227439812538 81
UVM_INFO @ 32224163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 54488740397408287981390030478783031379799174088615565983154649826233437268150 84
UVM_INFO @ 5893909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 103176638504892357956320181328661330426180230626271028708570939185144034257408 81
UVM_INFO @ 1910550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 63530204360277959792604370054969994304889608757466590379356820543284611615635 82
UVM_INFO @ 7496778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 67557931848546402807700186710636866639453250367059951303590019914044970808960 202
UVM_INFO @ 97627613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 63664302349177628818767877851346877132402888794451394585391687819035284669609 84
UVM_INFO @ 3117486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 14658871647532706563075764609356468056453197792538780333203248982922058239398 95
UVM_INFO @ 24111733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 17091665834317743081872944874879950664598551732860931093283338561466931185238 80
UVM_INFO @ 14718135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 86210788053319562756888760561652756846647451689738363134358376949116970961494 174
UVM_INFO @ 252558164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 62150972617715201081660290895222142107995880555703208895784068867532228290013 81
UVM_INFO @ 1452434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 38048933936738896238342359403371077654964377425622364419141737173297087142495 81
UVM_INFO @ 2294305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---