Simulation Results: csrng

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 76.63 %
  • code
  • 89.47 %
  • assert
  • 93.89 %
  • func
  • 46.54 %
  • block
  • 95.52 %
  • line
  • 96.13 %
  • branch
  • 89.15 %
  • toggle
  • 86.88 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 28.909us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 3.000s 227.482us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 21.679us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 27.000s 1337.256us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 48.584us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 70.152us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 21.679us 1 1 100.00
csrng_csr_aliasing 3.000s 48.584us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 2.000s 51.279us 1 1 100.00
alerts 1 1 100.00
csrng_alert 7.000s 248.185us 1 1 100.00
err 1 1 100.00
csrng_err 1.000s 23.951us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 3.000s 98.902us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 3.000s 98.902us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 2.000s 59.932us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 15.245us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 25.103us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 497.413us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 497.413us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 3.000s 227.482us 1 1 100.00
csrng_csr_rw 2.000s 21.679us 1 1 100.00
csrng_csr_aliasing 3.000s 48.584us 1 1 100.00
csrng_same_csr_outstanding 3.000s 51.702us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 3.000s 227.482us 1 1 100.00
csrng_csr_rw 2.000s 21.679us 1 1 100.00
csrng_csr_aliasing 3.000s 48.584us 1 1 100.00
csrng_same_csr_outstanding 3.000s 51.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 78.806us 1 1 100.00
csrng_tl_intg_err 4.000s 140.750us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 1.000s 4.795us 0 1 0.00
csrng_csr_rw 2.000s 21.679us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 7.000s 248.185us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 2.000s 59.932us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 2.000s 51.279us 1 1 100.00
csrng_err 1.000s 23.951us 1 1 100.00
csrng_sec_cm 3.000s 78.806us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 2.000s 51.279us 1 1 100.00
csrng_err 1.000s 23.951us 1 1 100.00
csrng_sec_cm 3.000s 78.806us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 2.000s 51.279us 1 1 100.00
csrng_err 1.000s 23.951us 1 1 100.00
csrng_sec_cm 3.000s 78.806us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 2.000s 51.279us 1 1 100.00
csrng_err 1.000s 23.951us 1 1 100.00
csrng_sec_cm 3.000s 78.806us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 2.000s 51.279us 1 1 100.00
csrng_err 1.000s 23.951us 1 1 100.00
csrng_sec_cm 3.000s 78.806us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 7.000s 248.185us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 2.000s 51.279us 1 1 100.00
csrng_err 1.000s 23.951us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 2.000s 59.932us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 7.000s 248.185us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 140.750us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 2.000s 51.279us 1 1 100.00
csrng_err 1.000s 23.951us 1 1 100.00
csrng_sec_cm 3.000s 78.806us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 2.000s 51.279us 1 1 100.00
csrng_err 1.000s 23.951us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 2.000s 51.279us 1 1 100.00
csrng_err 1.000s 23.951us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 2.000s 51.279us 1 1 100.00
csrng_err 1.000s 23.951us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 2.000s 51.279us 1 1 100.00
csrng_err 1.000s 23.951us 1 1 100.00
csrng_sec_cm 3.000s 78.806us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 2.000s 51.279us 1 1 100.00
csrng_err 1.000s 23.951us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.078s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 67406781855398737636313940153407324581218969362939365265068723374632389758642 100
UVM_INFO @ 98902441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 115321709936621418452811906761834828999757977344354591154473397381175037440975 99
UVM_INFO @ 4795222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 102212310142843230234637804496782020738644658020158933702529302454567152807059 None