Simulation Results: dma

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.40 %
  • code
  • 90.76 %
  • assert
  • 95.87 %
  • func
  • 63.56 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 362.686us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 278.313us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 1117.032us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 50.962us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 88.535us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 5.000s 446.547us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 80.906us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 3.000s 149.823us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 88.535us 1 1 100.00
dma_csr_aliasing 3.000s 80.906us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 65.000s 23360.928us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 652.000s 1280838.770us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 1400.000s 1075558.890us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 1400.000s 1075558.890us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 652.000s 1280838.770us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 172.000s 16895.855us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 1400.000s 1075558.890us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 6.000s 753.053us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 90.000s 31306.873us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 53.074us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 15.995us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 122.159us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 122.159us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 50.962us 1 1 100.00
dma_csr_rw 1.000s 88.535us 1 1 100.00
dma_csr_aliasing 3.000s 80.906us 1 1 100.00
dma_same_csr_outstanding 2.000s 84.976us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 50.962us 1 1 100.00
dma_csr_rw 1.000s 88.535us 1 1 100.00
dma_csr_aliasing 3.000s 80.906us 1 1 100.00
dma_same_csr_outstanding 2.000s 84.976us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 10.000s 65.005us 1 1 100.00
dma_generic_stress 172.000s 16895.855us 1 1 100.00
dma_handshake_stress 1400.000s 1075558.890us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 337.155us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 116.906us 1 1 100.00
dma_sec_cm 1.000s 58.837us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 90.000s 5138.178us 1 1 100.00
dma_longer_transfer 27.000s 1849.035us 1 1 100.00
dma_stress_all_with_rand_reset 2.000s 883.413us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 43072329073923453408917427809134557391149371349433932770104977795431994667186 92
UVM_INFO @ 883413359ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---