Simulation Results: edn/edn0

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 76.78 %
  • code
  • 85.91 %
  • assert
  • 94.91 %
  • func
  • 49.51 %
  • block
  • 94.43 %
  • line
  • 97.17 %
  • branch
  • 88.01 %
  • toggle
  • 74.73 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 57.483us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 18.112us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 23.123us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 8.000s 3359.482us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 98.041us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 56.549us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 23.123us 1 1 100.00
edn_csr_aliasing 2.000s 98.041us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 51.769us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 51.769us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 51.769us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 30.171us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 43.215us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 22.121us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 35.190us 1 1 100.00
edn_disable_auto_req_mode 2.000s 33.911us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.000s 1050.873us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 26.575us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 92.831us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.000s 141.051us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.000s 141.051us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 18.112us 1 1 100.00
edn_csr_rw 1.000s 23.123us 1 1 100.00
edn_csr_aliasing 2.000s 98.041us 1 1 100.00
edn_same_csr_outstanding 1.000s 22.310us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 18.112us 1 1 100.00
edn_csr_rw 1.000s 23.123us 1 1 100.00
edn_csr_aliasing 2.000s 98.041us 1 1 100.00
edn_same_csr_outstanding 1.000s 22.310us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.000s 265.856us 1 1 100.00
edn_tl_intg_err 2.000s 54.662us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 86.919us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 43.215us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 265.856us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 265.856us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 265.856us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 265.856us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 43.215us 1 1 100.00
edn_sec_cm 4.000s 265.856us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 43.215us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 54.662us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 33.000s 3287.385us 1 1 100.00