Simulation Results: edn/edn1

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.71 %
  • code
  • 80.77 %
  • assert
  • 98.70 %
  • func
  • 80.67 %
  • line
  • 97.50 %
  • branch
  • 91.34 %
  • cond
  • 86.69 %
  • toggle
  • 87.42 %
  • FSM
  • 40.91 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.880s 31.291us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.920s 34.462us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 40.038us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.710s 80.531us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.240s 24.312us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.960s 49.564us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 40.038us 1 1 100.00
edn_csr_aliasing 1.240s 24.312us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.590s 143.253us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.590s 143.253us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.590s 143.253us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.880s 28.380us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.350s 31.807us 1 1 100.00
errs 1 1 100.00
edn_err 1.120s 29.569us 1 1 100.00
disable 1 2 50.00
edn_disable 0.880s 14.478us 1 1 100.00
edn_disable_auto_req_mode 1.150s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 3.270s 275.896us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.760s 57.131us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.820s 13.625us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.020s 109.001us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.020s 109.001us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.920s 34.462us 1 1 100.00
edn_csr_rw 0.770s 40.038us 1 1 100.00
edn_csr_aliasing 1.240s 24.312us 1 1 100.00
edn_same_csr_outstanding 0.980s 25.154us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.920s 34.462us 1 1 100.00
edn_csr_rw 0.770s 40.038us 1 1 100.00
edn_csr_aliasing 1.240s 24.312us 1 1 100.00
edn_same_csr_outstanding 0.980s 25.154us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.690s 694.031us 1 1 100.00
edn_tl_intg_err 1.830s 314.467us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.990s 31.529us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.350s 31.807us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.690s 694.031us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.690s 694.031us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.690s 694.031us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.690s 694.031us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.350s 31.807us 1 1 100.00
edn_sec_cm 2.690s 694.031us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.350s 31.807us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.830s 314.467us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 48.620s 3228.292us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 83842983933406079109301270412436625274106870150061077840981210377334357382795 95
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---