Simulation Results: entropy_src/rng_16bits

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 69.90 %
  • code
  • 82.43 %
  • assert
  • 74.20 %
  • func
  • 53.06 %
  • block
  • 94.18 %
  • line
  • 97.82 %
  • branch
  • 86.22 %
  • toggle
  • 52.97 %
  • FSM
  • 92.71 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 1.000s 19.395us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 50.625us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 93.523us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 15.000s 4613.340us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 5.000s 757.626us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 29.507us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 93.523us 1 1 100.00
entropy_src_csr_aliasing 5.000s 757.626us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 1.000s 19.395us 1 1 100.00
entropy_src_rng 78.000s 13244.830us 1 1 100.00
entropy_src_fw_ov 326.000s 14081.246us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 326.000s 14081.246us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 78.000s 13244.830us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 121.000s 13120.143us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 78.000s 13244.830us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 78.000s 13244.830us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 78.000s 13244.830us 1 1 100.00
entropy_src_intr 20.000s 4143.593us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 78.000s 13244.830us 1 1 100.00
entropy_src_functional_alerts 5.000s 183.848us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 2.000s 81.827us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 63.482us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 10.000s 1132.730us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 39.603us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 143.124us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 70.326us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 70.326us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 50.625us 1 1 100.00
entropy_src_csr_rw 2.000s 93.523us 1 1 100.00
entropy_src_csr_aliasing 5.000s 757.626us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 46.292us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 50.625us 1 1 100.00
entropy_src_csr_rw 2.000s 93.523us 1 1 100.00
entropy_src_csr_aliasing 5.000s 757.626us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 46.292us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 95.375us 1 1 100.00
entropy_src_tl_intg_err 4.000s 104.268us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 78.000s 13244.830us 1 1 100.00
entropy_src_cfg_regwen 2.000s 16.766us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 78.000s 13244.830us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 78.000s 13244.830us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 78.000s 13244.830us 1 1 100.00
entropy_src_fw_ov 326.000s 14081.246us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 63.482us 1 1 100.00
entropy_src_sec_cm 3.000s 95.375us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 63.482us 1 1 100.00
entropy_src_sec_cm 3.000s 95.375us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 78.000s 13244.830us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 63.482us 1 1 100.00
entropy_src_sec_cm 3.000s 95.375us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 63.482us 1 1 100.00
entropy_src_sec_cm 3.000s 95.375us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 63.482us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 183.848us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 104.268us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 276.000s 13048.561us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 16.000s 766.770us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 85118252207977610205230704887162256006731740765905331751492736551387702345034 121
UVM_INFO @ 766770323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror alert_fail_counts 1 test run
entropy_src_csr_mem_rw_with_rand_reset 63253420914261719747368607727574967686089914420388067078298230378733936161930 113
UVM_INFO @ 29507333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---