Simulation Results: hmac

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.33 %
  • code
  • 95.88 %
  • assert
  • 97.17 %
  • func
  • 29.92 %
  • block
  • 97.37 %
  • line
  • 98.35 %
  • branch
  • 93.40 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 9.000s 5065.095us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 40.876us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 15.338us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 13.000s 1836.516us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 394.705us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 25.462us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 15.338us 1 1 100.00
hmac_csr_aliasing 3.000s 394.705us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 48.000s 5086.424us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 21.000s 2302.837us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 198.000s 56459.988us 1 1 100.00
hmac_test_sha384_vectors 22.000s 776.449us 1 1 100.00
hmac_test_sha512_vectors 27.000s 1412.343us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 1323.819us 1 1 100.00
hmac_test_hmac384_vectors 10.000s 389.697us 1 1 100.00
hmac_test_hmac512_vectors 13.000s 397.441us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 25.000s 2211.185us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 327.000s 42757.682us 1 1 100.00
error 1 1 100.00
hmac_error 7.000s 852.173us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 87.000s 35697.717us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 9.000s 5065.095us 1 1 100.00
hmac_long_msg 48.000s 5086.424us 1 1 100.00
hmac_back_pressure 21.000s 2302.837us 1 1 100.00
hmac_datapath_stress 327.000s 42757.682us 1 1 100.00
hmac_burst_wr 25.000s 2211.185us 1 1 100.00
hmac_stress_all 570.000s 267504.037us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 9.000s 5065.095us 1 1 100.00
hmac_long_msg 48.000s 5086.424us 1 1 100.00
hmac_back_pressure 21.000s 2302.837us 1 1 100.00
hmac_datapath_stress 327.000s 42757.682us 1 1 100.00
hmac_wipe_secret 87.000s 35697.717us 1 1 100.00
hmac_test_sha256_vectors 198.000s 56459.988us 1 1 100.00
hmac_test_sha384_vectors 22.000s 776.449us 1 1 100.00
hmac_test_sha512_vectors 27.000s 1412.343us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 1323.819us 1 1 100.00
hmac_test_hmac384_vectors 10.000s 389.697us 1 1 100.00
hmac_test_hmac512_vectors 13.000s 397.441us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 9.000s 5065.095us 1 1 100.00
hmac_long_msg 48.000s 5086.424us 1 1 100.00
hmac_back_pressure 21.000s 2302.837us 1 1 100.00
hmac_datapath_stress 327.000s 42757.682us 1 1 100.00
hmac_burst_wr 25.000s 2211.185us 1 1 100.00
hmac_error 7.000s 852.173us 1 1 100.00
hmac_wipe_secret 87.000s 35697.717us 1 1 100.00
hmac_test_sha256_vectors 198.000s 56459.988us 1 1 100.00
hmac_test_sha384_vectors 22.000s 776.449us 1 1 100.00
hmac_test_sha512_vectors 27.000s 1412.343us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 1323.819us 1 1 100.00
hmac_test_hmac384_vectors 10.000s 389.697us 1 1 100.00
hmac_test_hmac512_vectors 13.000s 397.441us 1 1 100.00
hmac_stress_all 570.000s 267504.037us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 570.000s 267504.037us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 13.450us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 2.000s 14.100us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 109.577us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 109.577us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 40.876us 1 1 100.00
hmac_csr_rw 1.000s 15.338us 1 1 100.00
hmac_csr_aliasing 3.000s 394.705us 1 1 100.00
hmac_same_csr_outstanding 2.000s 38.467us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 40.876us 1 1 100.00
hmac_csr_rw 1.000s 15.338us 1 1 100.00
hmac_csr_aliasing 3.000s 394.705us 1 1 100.00
hmac_same_csr_outstanding 2.000s 38.467us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 61.653us 1 1 100.00
hmac_tl_intg_err 3.000s 100.537us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.000s 100.537us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 9.000s 5065.095us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.000s 58.422us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 29.000s 2688.176us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 425.815us 1 1 100.00